Searched refs:null_surface_state (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c1686 state->null_surface_state = next_state;
2618 surface_state = cmd_buffer->state.null_surface_state;
2623 surface_state = cmd_buffer->state.null_surface_state;
2733 surface_state = cmd_buffer->device->null_surface_state;
2790 surface_state = cmd_buffer->device->null_surface_state;
2806 surface_state = cmd_buffer->device->null_surface_state;
2845 surface_state = cmd_buffer->device->null_surface_state;
2861 surface_state = cmd_buffer->device->null_surface_state;
6243 cmd_state->null_surface_state.map,
6367 cmd_state->null_surface_state
[all...]
H A Danv_device.c3230 device->null_surface_state =
3234 isl_null_fill_state(&device->isl_dev, device->null_surface_state.map,
3236 assert(device->null_surface_state.offset == 0);
H A Danv_private.h1199 struct anv_state null_surface_state; member in struct:anv_device
3056 struct anv_state null_surface_state; member in struct:anv_cmd_state
H A Danv_blorp.c1311 cmd_buffer->state.null_surface_state,
H A Danv_image.c2673 device->null_surface_state;
2695 * device->null_surface_state which always has offset == 0. We don't
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_cmd_buffer.c1182 state->null_surface_state = next_state;
1206 isl_null_fill_state(isl_dev, state->null_surface_state.map,
2094 surface_state = cmd_buffer->state.null_surface_state;
2099 surface_state = cmd_buffer->state.null_surface_state;
H A Danv_blorp.c1100 cmd_buffer->state.null_surface_state,
H A Danv_private.h2396 struct anv_state null_surface_state; member in struct:anv_cmd_state

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