Searched refs:num_channels (Results 1 - 25 of 63) sorted by last modified time

123

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Dradeon_kms.c523 info->num_channels = 1;
526 info->num_channels = 2;
529 info->num_channels = 4;
532 info->num_channels = 8;
567 info->num_channels = 1;
570 info->num_channels = 2;
573 info->num_channels = 4;
576 info->num_channels = 8;
H A Dradeon.h1027 int num_channels; member in struct:__anonb194aea90e08
H A Ddrmmode_display.c1170 height_align = info->num_channels * 8;
1234 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Dradeon_kms.c1603 info->num_channels = 1;
1606 info->num_channels = 2;
1609 info->num_channels = 4;
1612 info->num_channels = 8;
1647 info->num_channels = 1;
1650 info->num_channels = 2;
1653 info->num_channels = 4;
1656 info->num_channels = 8;
H A Dradeon.h588 int num_channels; member in struct:__anon5a499fe10208
H A Ddrmmode_display.c2329 height_align = info->num_channels * 8;
2395 base_align = MAX(info->num_banks * info->num_channels * 8 * 8 * bpe,
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Dglformats.c3605 int num_channels = 0, type_size = 0; local in function:_mesa_format_from_format_and_type
3672 num_channels = _mesa_components_in_format(format);
3675 normalized, num_channels,
H A Dformat_info.py48 elif fmat.has_channel('a') and fmat.num_channels() == 1:
57 elif fmat.has_channel('i') and fmat.num_channels() == 1:
H A Dformat_parser.py326 def num_channels(self): member in class:Format
338 considered to be an array of num_channels() channels identical to the
H A Dformats.c242 int num_channels; local in function:get_base_format_for_array_format
254 num_channels = _mesa_array_format_get_num_channels(format);
256 switch (num_channels) {
401 int num_channels; local in function:_mesa_array_format_flip_channels
404 num_channels = _mesa_array_format_get_num_channels(format);
407 if (num_channels == 1 || num_channels == 3)
410 if (num_channels == 2) {
422 if (num_channels == 4) {
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_eu_emit.c3117 brw_surface_payload_size(unsigned num_channels, argument
3123 return num_channels;
3125 return 2 * num_channels;
3171 unsigned num_channels)
3180 brw_surface_payload_size(num_channels, exec_size);
3183 brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, false);
3193 unsigned num_channels,
3207 brw_dp_untyped_surface_rw_desc(devinfo, exec_size, num_channels, true);
3166 brw_untyped_surface_read(struct brw_codegen * p,struct brw_reg dst,struct brw_reg payload,struct brw_reg surface,unsigned msg_length,unsigned num_channels) argument
3189 brw_untyped_surface_write(struct brw_codegen * p,struct brw_reg payload,struct brw_reg surface,unsigned msg_length,unsigned num_channels,bool header_present) argument
H A Dbrw_eu.h677 brw_mdc_cmask(unsigned num_channels) argument
680 return 0xf & (0xf << num_channels);
684 lsc_cmask(unsigned num_channels) argument
686 assert(num_channels > 0 && num_channels <= 4);
687 return BITSET_MASK(num_channels);
693 unsigned num_channels,
723 SET_BITS(brw_mdc_cmask(num_channels), 3, 0) |
819 unsigned num_channels,
834 SET_BITS(brw_mdc_cmask(num_channels),
691 brw_dp_untyped_surface_rw_desc(const struct intel_device_info * devinfo,unsigned exec_size,unsigned num_channels,bool write) argument
817 brw_dp_a64_untyped_surface_rw_desc(const struct intel_device_info * devinfo,unsigned exec_size,unsigned num_channels,bool write) argument
985 brw_dp_typed_surface_rw_desc(const struct intel_device_info * devinfo,unsigned exec_size,unsigned exec_group,unsigned num_channels,bool write) argument
1252 lsc_msg_desc(UNUSED const struct intel_device_info * devinfo,enum lsc_opcode opcode,unsigned simd_size,enum lsc_addr_surface_type addr_type,enum lsc_addr_size addr_sz,unsigned num_coordinates,enum lsc_data_size data_sz,unsigned num_channels,bool transpose,unsigned cache_ctrl,bool has_dest) argument
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/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/amdgpu/drm/
H A Damdgpu_surface.c90 config.info.num_channels = util_format_get_nr_components(tex->format);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/llvmpipe/
H A Dlp_bld_blend_aos.c233 unsigned num_channels)
242 swizzled_rgb = lp_build_swizzle_scalar_aos(&bld->base, rgb, alpha_swizzle, num_channels);
252 num_channels);
266 unsigned num_channels)
271 if (alpha_swizzle == PIPE_SWIZZLE_X && num_channels == 1) {
281 alpha_swizzle, num_channels);
228 lp_build_blend_swizzle(struct lp_build_blend_aos_context * bld,LLVMValueRef rgb,LLVMValueRef alpha,enum lp_build_blend_swizzle rgb_swizzle,unsigned alpha_swizzle,unsigned num_channels) argument
262 lp_build_blend_factor(struct lp_build_blend_aos_context * bld,unsigned rgb_factor,unsigned alpha_factor,unsigned alpha_swizzle,unsigned num_channels) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/vl/
H A Dvl_mpeg12_decoder.c937 unsigned num_channels; local in function:init_zscan
946 num_channels = dec->base.entrypoint <= PIPE_VIDEO_ENTRYPOINT_IDCT ? 4 : 1;
949 dec->blocks_per_line, dec->num_blocks, num_channels))
953 dec->blocks_per_line, dec->num_blocks, num_channels))
H A Dvl_zscan.c134 o_vtex = MALLOC(zscan->num_channels * sizeof(struct ureg_dst));
148 for (i = 0; i < zscan->num_channels; ++i)
173 for (i = 0; i < zscan->num_channels; ++i) {
176 * ((signed)i - (signed)zscan->num_channels / 2)));
211 vtex = MALLOC(zscan->num_channels * sizeof(struct ureg_src));
212 tmp = MALLOC(zscan->num_channels * sizeof(struct ureg_dst));
214 for (i = 0; i < zscan->num_channels; ++i)
221 for (i = 0; i < zscan->num_channels; ++i)
232 for (i = 0; i < zscan->num_channels; ++i)
235 for (i = 0; i < zscan->num_channels;
450 vl_zscan_init(struct vl_zscan * zscan,struct pipe_context * pipe,unsigned buffer_width,unsigned buffer_height,unsigned blocks_per_line,unsigned blocks_total,unsigned num_channels) argument
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H A Dvl_zscan.h45 unsigned num_channels; member in struct:vl_zscan
81 unsigned num_channels);
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/util/
H A Du_blitter.c2553 unsigned num_channels,
2562 assert(num_channels >= 1);
2563 assert(num_channels <= 4);
2583 u_upload_data(pipe->stream_uploader, 0, num_channels*4, 4, clear_value,
2596 ctx->velem_state_readbuf[num_channels-1]);
2597 bind_vs_pos_only(ctx, num_channels);
2550 util_blitter_clear_buffer(struct blitter_context * blitter,struct pipe_resource * dst,unsigned offset,unsigned size,unsigned num_channels,const union pipe_color_union * clear_value) argument
H A Du_blitter.h317 * "num_channels" can be 1, 2, 3, or 4, and specifies if the clear value is
320 * For each element, only "num_channels" components of "clear_value" are
321 * copied to the buffer, then the offset is incremented by num_channels*4.
326 unsigned num_channels,
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_swizzle.c159 unsigned num_channels)
166 if(a == bld->undef || a == bld->zero || a == bld->one || num_channels == 1)
169 assert(num_channels == 2 || num_channels == 4);
182 for(j = 0; j < n; j += num_channels)
183 for(i = 0; i < num_channels; ++i)
188 else if (num_channels == 2) {
203 type, 1 << channel, num_channels), "");
156 lp_build_swizzle_scalar_aos(struct lp_build_context * bld,LLVMValueRef a,unsigned channel,unsigned num_channels) argument
H A Dlp_bld_swizzle.h77 unsigned num_channels);
H A Dlp_bld_logic.c438 unsigned num_channels)
472 for(j = 0; j < n; j += num_channels)
473 for(i = 0; i < num_channels; ++i)
481 LLVMValueRef mask_vec = lp_build_const_mask_aos(bld->gallivm, type, mask, num_channels);
434 lp_build_select_aos(struct lp_build_context * bld,unsigned mask,LLVMValueRef a,LLVMValueRef b,unsigned num_channels) argument
H A Dlp_bld_logic.h92 unsigned num_channels);
/xsrc/external/mit/MesaLib/dist/src/compiler/nir/
H A Dnir_builder.h686 unsigned num_channels = 0, swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 }; local in function:nir_channels
691 swizzle[num_channels++] = i;
694 return nir_swizzle(b, def, swizzle, num_channels);
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_nir_to_llvm.c648 unsigned num_channels, bool is_float)
657 if (num_channels == 4 && num_channels == vec_size)
660 num_channels = MIN2(num_channels, vec_size);
662 for (unsigned i = 0; i < num_channels; i++)
665 assert(num_channels == 1);
669 for (unsigned i = num_channels; i < 4; i++) {
720 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels); local in function:load_vs_input
647 radv_fixup_vertex_input_fetches(struct radv_shader_context * ctx,LLVMValueRef value,unsigned num_channels,bool is_float) argument
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