1/* 2 * Copyright © 2009 Red Hat, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 * SOFTWARE. 22 * 23 * Authors: 24 * Dave Airlie <airlied@redhat.com> 25 * 26 */ 27#ifdef HAVE_CONFIG_H 28#include "config.h" 29#endif 30 31#include <errno.h> 32#include <sys/ioctl.h> 33/* Driver data structures */ 34#include "radeon.h" 35#include "radeon_bo_helper.h" 36#include "radeon_drm_queue.h" 37#include "radeon_glamor.h" 38#include "radeon_reg.h" 39#include "radeon_probe.h" 40#include "micmap.h" 41#include "mipointrst.h" 42 43#include "radeon_version.h" 44#include "shadow.h" 45#include <xf86Priv.h> 46 47#include "atipciids.h" 48 49#if HAVE_PRESENT_H 50#include <present.h> 51#endif 52 53/* DPMS */ 54#ifdef HAVE_XEXTPROTO_71 55#include <X11/extensions/dpmsconst.h> 56#else 57#define DPMS_SERVER 58#include <X11/extensions/dpms.h> 59#endif 60 61#include <X11/extensions/damageproto.h> 62 63#include "radeon_chipinfo_gen.h" 64 65#include "radeon_bo_gem.h" 66#include "radeon_cs_gem.h" 67#include "radeon_vbo.h" 68 69static DevScreenPrivateKeyRec radeon_client_private_key; 70DevScreenPrivateKeyRec radeon_device_private_key; 71 72extern SymTabRec RADEONChipsets[]; 73static Bool radeon_setup_kernel_mem(ScreenPtr pScreen); 74 75const OptionInfoRec RADEONOptions_KMS[] = { 76 { OPTION_ACCEL, "Accel", OPTV_BOOLEAN, {0}, FALSE }, 77 { OPTION_SW_CURSOR, "SWcursor", OPTV_BOOLEAN, {0}, FALSE }, 78 { OPTION_PAGE_FLIP, "EnablePageFlip", OPTV_BOOLEAN, {0}, FALSE }, 79 { OPTION_COLOR_TILING, "ColorTiling", OPTV_BOOLEAN, {0}, FALSE }, 80 { OPTION_COLOR_TILING_2D,"ColorTiling2D", OPTV_BOOLEAN, {0}, FALSE }, 81 { OPTION_RENDER_ACCEL, "RenderAccel", OPTV_BOOLEAN, {0}, FALSE }, 82 { OPTION_SUBPIXEL_ORDER, "SubPixelOrder", OPTV_ANYSTR, {0}, FALSE }, 83#ifdef USE_GLAMOR 84 { OPTION_ACCELMETHOD, "AccelMethod", OPTV_STRING, {0}, FALSE }, 85 { OPTION_SHADOW_PRIMARY, "ShadowPrimary", OPTV_BOOLEAN, {0}, FALSE }, 86#endif 87 { OPTION_EXA_VSYNC, "EXAVSync", OPTV_BOOLEAN, {0}, FALSE }, 88 { OPTION_EXA_PIXMAPS, "EXAPixmaps", OPTV_BOOLEAN, {0}, FALSE }, 89 { OPTION_ZAPHOD_HEADS, "ZaphodHeads", OPTV_STRING, {0}, FALSE }, 90 { OPTION_SWAPBUFFERS_WAIT,"SwapbuffersWait", OPTV_BOOLEAN, {0}, FALSE }, 91 { OPTION_DELETE_DP12, "DeleteUnusedDP12Displays", OPTV_BOOLEAN, {0}, FALSE}, 92 { OPTION_DRI3, "DRI3", OPTV_BOOLEAN, {0}, FALSE }, 93 { OPTION_DRI, "DRI", OPTV_INTEGER, {0}, FALSE }, 94 { OPTION_TEAR_FREE, "TearFree", OPTV_BOOLEAN, {0}, FALSE }, 95 { -1, NULL, OPTV_NONE, {0}, FALSE } 96}; 97 98const OptionInfoRec *RADEONOptionsWeak(void) { return RADEONOptions_KMS; } 99 100void radeon_cs_flush_indirect(ScrnInfoPtr pScrn) 101{ 102 RADEONInfoPtr info = RADEONPTR(pScrn); 103 struct radeon_accel_state *accel_state; 104 int ret; 105 106 info->gpu_flushed++; 107 108#ifdef USE_GLAMOR 109 if (info->use_glamor) { 110 glamor_block_handler(pScrn->pScreen); 111 return; 112 } 113#endif 114 115 if (!info->cs->cdw) 116 return; 117 118 accel_state = info->accel_state; 119 120 /* release the current VBO so we don't block on mapping it later */ 121 if (info->accel_state->vbo.vb_offset && info->accel_state->vbo.vb_bo) { 122 radeon_vbo_put(pScrn, &info->accel_state->vbo); 123 info->accel_state->vbo.vb_start_op = -1; 124 } 125 126 /* release the current VBO so we don't block on mapping it later */ 127 if (info->accel_state->cbuf.vb_bo) { 128 radeon_vbo_put(pScrn, &info->accel_state->cbuf); 129 info->accel_state->cbuf.vb_start_op = -1; 130 } 131 132 radeon_cs_emit(info->cs); 133 radeon_cs_erase(info->cs); 134 135 if (accel_state->use_vbos) 136 radeon_vbo_flush_bos(pScrn); 137 138 ret = radeon_cs_space_check_with_bo(info->cs, 139 accel_state->vbo.vb_bo, 140 RADEON_GEM_DOMAIN_GTT, 0); 141 if (ret) 142 ErrorF("space check failed in flush\n"); 143 144 if (info->reemit_current2d && info->state_2d.op) 145 info->reemit_current2d(pScrn, info->state_2d.op); 146 147 if (info->dri2.enabled) { 148 info->accel_state->XInited3D = FALSE; 149 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 150 } 151 152} 153 154void radeon_ddx_cs_start(ScrnInfoPtr pScrn, 155 int n, const char *file, 156 const char *func, int line) 157{ 158 RADEONInfoPtr info = RADEONPTR(pScrn); 159 160 if (info->cs->cdw + n > info->cs->ndw) { 161 radeon_cs_flush_indirect(pScrn); 162 163 } 164 radeon_cs_begin(info->cs, n, file, func, line); 165} 166 167 168extern _X_EXPORT int gRADEONEntityIndex; 169 170static int getRADEONEntityIndex(void) 171{ 172 return gRADEONEntityIndex; 173} 174 175 176RADEONEntPtr RADEONEntPriv(ScrnInfoPtr pScrn) 177{ 178 DevUnion *pPriv; 179 RADEONInfoPtr info = RADEONPTR(pScrn); 180 pPriv = xf86GetEntityPrivate(info->pEnt->index, 181 getRADEONEntityIndex()); 182 return pPriv->ptr; 183} 184 185/* Allocate our private RADEONInfoRec */ 186static Bool RADEONGetRec(ScrnInfoPtr pScrn) 187{ 188 if (pScrn->driverPrivate) return TRUE; 189 190 pScrn->driverPrivate = xnfcalloc(sizeof(RADEONInfoRec), 1); 191 return TRUE; 192} 193 194/* Free our private RADEONInfoRec */ 195static void RADEONFreeRec(ScrnInfoPtr pScrn) 196{ 197 DevUnion *pPriv; 198 RADEONEntPtr pRADEONEnt; 199 RADEONInfoPtr info; 200 EntityInfoPtr pEnt; 201 202 if (!pScrn) 203 return; 204 205 pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 206 pPriv = xf86GetEntityPrivate(pEnt->index, gRADEONEntityIndex); 207 pRADEONEnt = pPriv->ptr; 208 209 info = RADEONPTR(pScrn); 210 if (info) { 211 if (info->fbcon_pixmap) 212 pScrn->pScreen->DestroyPixmap(info->fbcon_pixmap); 213 214 if (info->accel_state) { 215 free(info->accel_state); 216 info->accel_state = NULL; 217 } 218 219#ifdef USE_GLAMOR 220 if (info->gbm) 221 gbm_device_destroy(info->gbm); 222#endif 223 224 pRADEONEnt->scrn[info->instance_id] = NULL; 225 pRADEONEnt->num_scrns--; 226 free(pScrn->driverPrivate); 227 pScrn->driverPrivate = NULL; 228 } 229 230 if (pRADEONEnt->fd > 0) { 231 DevUnion *pPriv; 232 RADEONEntPtr pRADEONEnt; 233 pPriv = xf86GetEntityPrivate(pScrn->entityList[0], 234 getRADEONEntityIndex()); 235 236 pRADEONEnt = pPriv->ptr; 237 pRADEONEnt->fd_ref--; 238 if (!pRADEONEnt->fd_ref) { 239#ifdef XF86_PDEV_SERVER_FD 240 if (!(pRADEONEnt->platform_dev && 241 pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 242#endif 243 drmClose(pRADEONEnt->fd); 244 free(pPriv->ptr); 245 pPriv->ptr = NULL; 246 } 247 } 248 249 free(pEnt); 250} 251 252static void * 253radeonShadowWindow(ScreenPtr screen, CARD32 row, CARD32 offset, int mode, 254 CARD32 *size, void *closure) 255{ 256 ScrnInfoPtr pScrn = xf86ScreenToScrn(screen); 257 RADEONInfoPtr info = RADEONPTR(pScrn); 258 int stride; 259 260 stride = (pScrn->displayWidth * pScrn->bitsPerPixel) / 8; 261 *size = stride; 262 263 return ((uint8_t *)info->front_buffer->bo.radeon->ptr + row * stride + offset); 264} 265 266static void 267radeonUpdatePacked(ScreenPtr pScreen, shadowBufPtr pBuf) 268{ 269 shadowUpdatePacked(pScreen, pBuf); 270} 271 272static Bool 273callback_needs_flush(RADEONInfoPtr info, struct radeon_client_priv *client_priv) 274{ 275 return (int)(client_priv->needs_flush - info->gpu_flushed) > 0; 276} 277 278static void 279radeon_event_callback(CallbackListPtr *list, 280 pointer user_data, pointer call_data) 281{ 282 EventInfoRec *eventinfo = call_data; 283 ScrnInfoPtr pScrn = user_data; 284 ScreenPtr pScreen = pScrn->pScreen; 285 struct radeon_client_priv *client_priv = 286 dixLookupScreenPrivate(&eventinfo->client->devPrivates, 287 &radeon_client_private_key, pScreen); 288 struct radeon_client_priv *server_priv = 289 dixLookupScreenPrivate(&serverClient->devPrivates, 290 &radeon_client_private_key, pScreen); 291 RADEONInfoPtr info = RADEONPTR(pScrn); 292 int i; 293 294 if (callback_needs_flush(info, client_priv) || 295 callback_needs_flush(info, server_priv)) 296 return; 297 298 /* Don't let gpu_flushed get too far ahead of needs_flush, in order 299 * to prevent false positives in callback_needs_flush() 300 */ 301 client_priv->needs_flush = info->gpu_flushed; 302 server_priv->needs_flush = info->gpu_flushed; 303 304 for (i = 0; i < eventinfo->count; i++) { 305 if (eventinfo->events[i].u.u.type == info->callback_event_type) { 306 client_priv->needs_flush++; 307 server_priv->needs_flush++; 308 return; 309 } 310 } 311} 312 313static void 314radeon_flush_callback(CallbackListPtr *list, 315 pointer user_data, pointer call_data) 316{ 317 ScrnInfoPtr pScrn = user_data; 318 ScreenPtr pScreen = pScrn->pScreen; 319 ClientPtr client = call_data ? call_data : serverClient; 320 struct radeon_client_priv *client_priv = 321 dixLookupScreenPrivate(&client->devPrivates, 322 &radeon_client_private_key, pScreen); 323 RADEONInfoPtr info = RADEONPTR(pScrn); 324 325 if (pScrn->vtSema && callback_needs_flush(info, client_priv)) 326 radeon_cs_flush_indirect(pScrn); 327} 328 329static Bool RADEONCreateScreenResources_KMS(ScreenPtr pScreen) 330{ 331 ExtensionEntry *damage_ext; 332 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 333 RADEONInfoPtr info = RADEONPTR(pScrn); 334 PixmapPtr pixmap; 335 336 pScreen->CreateScreenResources = info->CreateScreenResources; 337 if (!(*pScreen->CreateScreenResources)(pScreen)) 338 return FALSE; 339 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 340 341 /* Set the RandR primary output if Xorg hasn't */ 342 if (dixPrivateKeyRegistered(rrPrivKey)) { 343 rrScrPrivPtr rrScrPriv = rrGetScrPriv(pScreen); 344 345 if (!pScreen->isGPU && !rrScrPriv->primaryOutput) { 346 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 347 348 rrScrPriv->primaryOutput = xf86_config->output[0]->randr_output; 349 RROutputChanged(rrScrPriv->primaryOutput, FALSE); 350 rrScrPriv->layoutChanged = TRUE; 351 } 352 353 drmmode_uevent_init(pScrn, &info->drmmode); 354 } 355 356 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, pScreen->isGPU)) 357 return FALSE; 358 359 if (info->r600_shadow_fb) { 360 pixmap = pScreen->GetScreenPixmap(pScreen); 361 362 if (!shadowAdd(pScreen, pixmap, radeonUpdatePacked, 363 radeonShadowWindow, 0, NULL)) 364 return FALSE; 365 } 366 367 if (info->dri2.enabled || info->use_glamor) { 368 if (info->front_buffer) { 369 PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen); 370 if (!radeon_set_pixmap_bo(pPix, info->front_buffer)) 371 return FALSE; 372 373 if (info->surf_man && !info->use_glamor) 374 *radeon_get_pixmap_surface(pPix) = info->front_surface; 375 } 376 } 377 378 if (info->use_glamor) 379 radeon_glamor_create_screen_resources(pScreen); 380 381 info->callback_event_type = -1; 382 if (!pScreen->isGPU && (damage_ext = CheckExtension("DAMAGE"))) { 383 info->callback_event_type = damage_ext->eventBase + XDamageNotify; 384 385 if (!AddCallback(&FlushCallback, radeon_flush_callback, pScrn)) 386 return FALSE; 387 388 if (!AddCallback(&EventCallback, radeon_event_callback, pScrn)) { 389 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 390 return FALSE; 391 } 392 393 if (!dixRegisterScreenPrivateKey(&radeon_client_private_key, pScreen, 394 PRIVATE_CLIENT, sizeof(struct radeon_client_priv))) { 395 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 396 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 397 return FALSE; 398 } 399 } 400 401 return TRUE; 402} 403 404static Bool 405radeon_scanout_extents_intersect(xf86CrtcPtr xf86_crtc, BoxPtr extents) 406{ 407 if (xf86_crtc->scrn->is_gpu) { 408 extents->x1 -= xf86_crtc->x; 409 extents->y1 -= xf86_crtc->y; 410 extents->x2 -= xf86_crtc->x; 411 extents->y2 -= xf86_crtc->y; 412 } else { 413 extents->x1 -= xf86_crtc->filter_width >> 1; 414 extents->x2 += xf86_crtc->filter_width >> 1; 415 extents->y1 -= xf86_crtc->filter_height >> 1; 416 extents->y2 += xf86_crtc->filter_height >> 1; 417 pixman_f_transform_bounds(&xf86_crtc->f_framebuffer_to_crtc, extents); 418 } 419 420 extents->x1 = max(extents->x1, 0); 421 extents->y1 = max(extents->y1, 0); 422 extents->x2 = min(extents->x2, xf86_crtc->mode.HDisplay); 423 extents->y2 = min(extents->y2, xf86_crtc->mode.VDisplay); 424 425 return (extents->x1 < extents->x2 && extents->y1 < extents->y2); 426} 427 428static RegionPtr 429transform_region(RegionPtr region, struct pict_f_transform *transform, 430 int w, int h) 431{ 432 BoxPtr boxes = RegionRects(region); 433 int nboxes = RegionNumRects(region); 434 xRectanglePtr rects = malloc(nboxes * sizeof(*rects)); 435 RegionPtr transformed; 436 int nrects = 0; 437 BoxRec box; 438 int i; 439 440 for (i = 0; i < nboxes; i++) { 441 box.x1 = boxes[i].x1; 442 box.x2 = boxes[i].x2; 443 box.y1 = boxes[i].y1; 444 box.y2 = boxes[i].y2; 445 pixman_f_transform_bounds(transform, &box); 446 447 box.x1 = max(box.x1, 0); 448 box.y1 = max(box.y1, 0); 449 box.x2 = min(box.x2, w); 450 box.y2 = min(box.y2, h); 451 if (box.x1 >= box.x2 || box.y1 >= box.y2) 452 continue; 453 454 rects[nrects].x = box.x1; 455 rects[nrects].y = box.y1; 456 rects[nrects].width = box.x2 - box.x1; 457 rects[nrects].height = box.y2 - box.y1; 458 nrects++; 459 } 460 461 transformed = RegionFromRects(nrects, rects, CT_UNSORTED); 462 free(rects); 463 return transformed; 464} 465 466static void 467radeon_sync_scanout_pixmaps(xf86CrtcPtr xf86_crtc, RegionPtr new_region, 468 int scanout_id) 469{ 470 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 471 DrawablePtr dst = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 472 DrawablePtr src = &drmmode_crtc->scanout[scanout_id ^ 1].pixmap->drawable; 473 RegionPtr last_region = &drmmode_crtc->scanout_last_region; 474 ScrnInfoPtr scrn = xf86_crtc->scrn; 475 ScreenPtr pScreen = scrn->pScreen; 476 RADEONInfoPtr info = RADEONPTR(scrn); 477 RegionRec remaining; 478 RegionPtr sync_region = NULL; 479 BoxRec extents; 480 Bool force; 481 GCPtr gc; 482 483 if (RegionNil(last_region)) 484 return; 485 486 RegionNull(&remaining); 487 RegionSubtract(&remaining, last_region, new_region); 488 if (RegionNil(&remaining)) 489 goto uninit; 490 491 extents = *RegionExtents(&remaining); 492 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 493 goto uninit; 494 495 if (xf86_crtc->driverIsPerformingTransform) { 496 sync_region = transform_region(&remaining, 497 &xf86_crtc->f_framebuffer_to_crtc, 498 dst->width, dst->height); 499 } else { 500 sync_region = RegionDuplicate(&remaining); 501 RegionTranslate(sync_region, -xf86_crtc->x, -xf86_crtc->y); 502 } 503 504 force = info->accel_state->force; 505 info->accel_state->force = TRUE; 506 507 gc = GetScratchGC(dst->depth, pScreen); 508 if (gc) { 509 gc->funcs->ChangeClip(gc, CT_REGION, sync_region, 0); 510 ValidateGC(dst, gc); 511 sync_region = NULL; 512 gc->ops->CopyArea(src, dst, gc, 0, 0, dst->width, dst->height, 0, 0); 513 FreeScratchGC(gc); 514 } 515 516 info->accel_state->force = force; 517 518 uninit: 519 if (sync_region) 520 RegionDestroy(sync_region); 521 RegionUninit(&remaining); 522} 523 524static void 525radeon_scanout_flip_abort(xf86CrtcPtr crtc, void *event_data) 526{ 527 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 528 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 529 struct drmmode_fb *fb = event_data; 530 531 drmmode_crtc->scanout_update_pending = 0; 532 533 if (drmmode_crtc->flip_pending == fb) { 534 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, 535 NULL); 536 } 537} 538 539static void 540radeon_scanout_flip_handler(xf86CrtcPtr crtc, uint32_t msc, uint64_t usec, 541 void *event_data) 542{ 543 RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn); 544 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 545 struct drmmode_fb *fb = event_data; 546 547 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, fb); 548 radeon_scanout_flip_abort(crtc, event_data); 549} 550 551 552static RegionPtr 553dirty_region(PixmapDirtyUpdatePtr dirty) 554{ 555 RegionPtr damageregion = DamageRegion(dirty->damage); 556 RegionPtr dstregion; 557 558#ifdef HAS_DIRTYTRACKING_ROTATION 559 if (dirty->rotation != RR_Rotate_0) { 560 dstregion = transform_region(damageregion, 561 &dirty->f_inverse, 562 dirty->secondary_dst->drawable.width, 563 dirty->secondary_dst->drawable.height); 564 } else 565#endif 566 { 567 RegionRec pixregion; 568 569 dstregion = RegionDuplicate(damageregion); 570 RegionTranslate(dstregion, -dirty->x, -dirty->y); 571 PixmapRegionInit(&pixregion, dirty->secondary_dst); 572 RegionIntersect(dstregion, dstregion, &pixregion); 573 RegionUninit(&pixregion); 574 } 575 576 return dstregion; 577} 578 579static void 580redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region) 581{ 582 ScrnInfoPtr src_scrn = 583 xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen); 584 585 if (RegionNil(region)) 586 goto out; 587 588 if (dirty->secondary_dst->primary_pixmap) 589 DamageRegionAppend(&dirty->secondary_dst->drawable, region); 590 591#ifdef HAS_DIRTYTRACKING_ROTATION 592 PixmapSyncDirtyHelper(dirty); 593#else 594 PixmapSyncDirtyHelper(dirty, region); 595#endif 596 597 radeon_cs_flush_indirect(src_scrn); 598 if (dirty->secondary_dst->primary_pixmap) 599 DamageRegionProcessPending(&dirty->secondary_dst->drawable); 600 601out: 602 DamageEmpty(dirty->damage); 603} 604 605static void 606radeon_prime_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 607{ 608 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 609 610 drmmode_crtc->scanout_update_pending = 0; 611} 612 613void 614radeon_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 615{ 616 ScreenPtr primary_screen = radeon_dirty_primary(dirty); 617 PixmapDirtyUpdatePtr ent; 618 RegionPtr region; 619 620 xorg_list_for_each_entry(ent, &primary_screen->pixmap_dirty_list, ent) { 621 if (!radeon_dirty_src_equals(dirty, ent->secondary_dst)) 622 continue; 623 624 region = dirty_region(ent); 625 redisplay_dirty(ent, region); 626 RegionDestroy(region); 627 } 628} 629 630 631#if HAS_SYNC_SHARED_PIXMAP 632 633static Bool 634primary_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 635{ 636 ScreenPtr primary_screen = radeon_dirty_primary(dirty); 637 638 return !!primary_screen->SyncSharedPixmap; 639} 640 641static Bool 642secondary_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 643{ 644 ScreenPtr secondary_screen = dirty->secondary_dst->drawable.pScreen; 645 646 return !!secondary_screen->SyncSharedPixmap; 647} 648 649static void 650call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 651{ 652 ScreenPtr primary_screen = radeon_dirty_primary(dirty); 653 654 primary_screen->SyncSharedPixmap(dirty); 655} 656 657#else /* !HAS_SYNC_SHARED_PIXMAP */ 658 659static Bool 660primary_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 661{ 662 ScrnInfoPtr primary_scrn = xf86ScreenToScrn(radeon_dirty_primary(dirty)); 663 664 return primary_scrn->driverName == scrn->driverName; 665} 666 667static Bool 668secondary_has_sync_shared_pixmap(ScrnInfoPtr scrn, PixmapDirtyUpdatePtr dirty) 669{ 670 ScrnInfoPtr secondary_scrn = xf86ScreenToScrn(dirty->secondary_dst->drawable.pScreen); 671 672 return secondary_scrn->driverName == scrn->driverName; 673} 674 675static void 676call_sync_shared_pixmap(PixmapDirtyUpdatePtr dirty) 677{ 678 radeon_sync_shared_pixmap(dirty); 679} 680 681#endif /* HAS_SYNC_SHARED_PIXMAPS */ 682 683 684static xf86CrtcPtr 685radeon_prime_dirty_to_crtc(PixmapDirtyUpdatePtr dirty) 686{ 687 ScreenPtr screen = dirty->secondary_dst->drawable.pScreen; 688 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 689 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 690 int c; 691 692 /* Find the CRTC which is scanning out from this secondary pixmap */ 693 for (c = 0; c < xf86_config->num_crtc; c++) { 694 xf86CrtcPtr xf86_crtc = xf86_config->crtc[c]; 695 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 696 697 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) 698 return xf86_crtc; 699 } 700 701 return NULL; 702} 703 704static Bool 705radeon_prime_scanout_do_update(xf86CrtcPtr crtc, unsigned scanout_id) 706{ 707 ScrnInfoPtr scrn = crtc->scrn; 708 ScreenPtr screen = scrn->pScreen; 709 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 710 PixmapDirtyUpdatePtr dirty; 711 Bool ret = FALSE; 712 713 xorg_list_for_each_entry(dirty, &screen->pixmap_dirty_list, ent) { 714 if (radeon_dirty_src_equals(dirty, drmmode_crtc->prime_scanout_pixmap)) { 715 RegionPtr region; 716 717 if (primary_has_sync_shared_pixmap(scrn, dirty)) 718 call_sync_shared_pixmap(dirty); 719 720 region = dirty_region(dirty); 721 if (RegionNil(region)) 722 goto destroy; 723 724 if (drmmode_crtc->tear_free) { 725 RegionTranslate(region, crtc->x, crtc->y); 726 radeon_sync_scanout_pixmaps(crtc, region, scanout_id); 727 radeon_cs_flush_indirect(scrn); 728 RegionCopy(&drmmode_crtc->scanout_last_region, region); 729 RegionTranslate(region, -crtc->x, -crtc->y); 730 dirty->secondary_dst = drmmode_crtc->scanout[scanout_id].pixmap; 731 } 732 733 redisplay_dirty(dirty, region); 734 ret = TRUE; 735 destroy: 736 RegionDestroy(region); 737 break; 738 } 739 } 740 741 return ret; 742} 743 744static void 745radeon_prime_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 746 void *event_data) 747{ 748 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 749 750 radeon_prime_scanout_do_update(crtc, 0); 751 drmmode_crtc->scanout_update_pending = 0; 752} 753 754static void 755radeon_prime_scanout_update(PixmapDirtyUpdatePtr dirty) 756{ 757 ScreenPtr screen = dirty->secondary_dst->drawable.pScreen; 758 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 759 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 760 xf86CrtcPtr xf86_crtc = radeon_prime_dirty_to_crtc(dirty); 761 drmmode_crtc_private_ptr drmmode_crtc; 762 uintptr_t drm_queue_seq; 763 764 if (!xf86_crtc || !xf86_crtc->enabled) 765 return; 766 767 drmmode_crtc = xf86_crtc->driver_private; 768 if (drmmode_crtc->scanout_update_pending || 769 !drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap || 770 drmmode_crtc->dpms_mode != DPMSModeOn) 771 return; 772 773 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 774 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 775 RADEON_DRM_QUEUE_ID_DEFAULT, NULL, 776 radeon_prime_scanout_update_handler, 777 radeon_prime_scanout_update_abort, 778 FALSE); 779 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 780 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 781 "radeon_drm_queue_alloc failed for PRIME update\n"); 782 radeon_prime_scanout_update_handler(xf86_crtc, 0, 0, NULL); 783 return; 784 } 785 786 drmmode_crtc->scanout_update_pending = drm_queue_seq; 787 788 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 789 1, drm_queue_seq, NULL, NULL)) { 790 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) { 791 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 792 "drmmode_wait_vblank failed for PRIME update: %s\n", 793 strerror(errno)); 794 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED; 795 } 796 797 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd, 798 0, 0, 0, 799 (void*)drm_queue_seq); 800 drmmode_crtc->wait_flip_nesting_level++; 801 radeon_drm_queue_handle_deferred(xf86_crtc); 802 return; 803 } 804 805 if (drmmode_crtc->scanout_status == 806 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) { 807 /* The page flip and vblank ioctls failed before, but the vblank 808 * ioctl is working again, so we can try re-enabling TearFree 809 */ 810 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode, 811 xf86_crtc->rotation, 812 xf86_crtc->x, xf86_crtc->y); 813 } 814 815 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED; 816} 817 818static void 819radeon_prime_scanout_flip(PixmapDirtyUpdatePtr ent) 820{ 821 ScreenPtr screen = ent->secondary_dst->drawable.pScreen; 822 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 823 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 824 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 825 drmmode_crtc_private_ptr drmmode_crtc; 826 uintptr_t drm_queue_seq; 827 unsigned scanout_id; 828 struct drmmode_fb *fb; 829 830 if (!crtc || !crtc->enabled) 831 return; 832 833 drmmode_crtc = crtc->driver_private; 834 scanout_id = drmmode_crtc->scanout_id ^ 1; 835 if (drmmode_crtc->scanout_update_pending || 836 !drmmode_crtc->scanout[scanout_id].pixmap || 837 drmmode_crtc->dpms_mode != DPMSModeOn) 838 return; 839 840 if (!radeon_prime_scanout_do_update(crtc, scanout_id)) 841 return; 842 843 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 844 if (!fb) { 845 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 846 "Failed to get FB for PRIME flip.\n"); 847 return; 848 } 849 850 drm_queue_seq = radeon_drm_queue_alloc(crtc, 851 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 852 RADEON_DRM_QUEUE_ID_DEFAULT, fb, 853 radeon_scanout_flip_handler, 854 radeon_scanout_flip_abort, TRUE); 855 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 856 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 857 "Allocating DRM event queue entry failed for PRIME flip.\n"); 858 return; 859 } 860 861 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 862 fb->handle, 0, drm_queue_seq, 1) 863 != 0) { 864 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) { 865 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 866 "flip queue failed in %s: %s, TearFree inactive\n", 867 __func__, strerror(errno)); 868 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED; 869 } 870 871 radeon_drm_abort_entry(drm_queue_seq); 872 return; 873 } 874 875 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) { 876 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n"); 877 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED; 878 } 879 880 drmmode_crtc->scanout_id = scanout_id; 881 drmmode_crtc->scanout_update_pending = drm_queue_seq; 882 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb); 883} 884 885static void 886radeon_dirty_update(ScrnInfoPtr scrn) 887{ 888 ScreenPtr screen = scrn->pScreen; 889 PixmapDirtyUpdatePtr ent; 890 RegionPtr region; 891 892 xorg_list_for_each_entry(ent, &screen->pixmap_dirty_list, ent) { 893 if (screen->isGPU) { 894 PixmapDirtyUpdatePtr region_ent = ent; 895 896 if (primary_has_sync_shared_pixmap(scrn, ent)) { 897 ScreenPtr primary_screen = radeon_dirty_primary(ent); 898 899 xorg_list_for_each_entry(region_ent, &primary_screen->pixmap_dirty_list, ent) { 900 if (radeon_dirty_src_equals(ent, region_ent->secondary_dst)) 901 break; 902 } 903 } 904 905 region = dirty_region(region_ent); 906 907 if (RegionNotEmpty(region)) { 908 xf86CrtcPtr crtc = radeon_prime_dirty_to_crtc(ent); 909 drmmode_crtc_private_ptr drmmode_crtc = NULL; 910 911 if (crtc) 912 drmmode_crtc = crtc->driver_private; 913 914 if (drmmode_crtc && drmmode_crtc->tear_free) 915 radeon_prime_scanout_flip(ent); 916 else 917 radeon_prime_scanout_update(ent); 918 } else { 919 DamageEmpty(region_ent->damage); 920 } 921 922 RegionDestroy(region); 923 } else { 924 if (secondary_has_sync_shared_pixmap(scrn, ent)) 925 continue; 926 927 region = dirty_region(ent); 928 redisplay_dirty(ent, region); 929 RegionDestroy(region); 930 } 931 } 932} 933 934static void 935radeonSourceValidate(DrawablePtr draw, int x, int y, int w, int h, 936 unsigned int subWindowMode) 937{ 938} 939 940 941 942Bool 943radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int scanout_id, 944 PixmapPtr src_pix, BoxRec extents) 945{ 946 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 947 RegionRec region = { .extents = extents, .data = NULL }; 948 ScrnInfoPtr scrn = xf86_crtc->scrn; 949 ScreenPtr pScreen = scrn->pScreen; 950 RADEONInfoPtr info = RADEONPTR(scrn); 951 DrawablePtr pDraw; 952 Bool force; 953 954 if (!xf86_crtc->enabled || 955 !drmmode_crtc->scanout[scanout_id].pixmap || 956 extents.x1 >= extents.x2 || extents.y1 >= extents.y2) 957 return FALSE; 958 959 pDraw = &drmmode_crtc->scanout[scanout_id].pixmap->drawable; 960 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) 961 return FALSE; 962 963 if (drmmode_crtc->tear_free) { 964 radeon_sync_scanout_pixmaps(xf86_crtc, ®ion, scanout_id); 965 RegionCopy(&drmmode_crtc->scanout_last_region, ®ion); 966 } 967 968 force = info->accel_state->force; 969 info->accel_state->force = TRUE; 970 971 if (xf86_crtc->driverIsPerformingTransform) { 972 SourceValidateProcPtr SourceValidate = pScreen->SourceValidate; 973 PictFormatPtr format = PictureWindowFormat(pScreen->root); 974 int error; 975 PicturePtr src, dst; 976 977 src = CreatePicture(None, &src_pix->drawable, format, 0L, NULL, 978 serverClient, &error); 979 if (!src) { 980 ErrorF("Failed to create source picture for transformed scanout " 981 "update\n"); 982 goto out; 983 } 984 985 dst = CreatePicture(None, pDraw, format, 0L, NULL, serverClient, &error); 986 if (!dst) { 987 ErrorF("Failed to create destination picture for transformed scanout " 988 "update\n"); 989 goto free_src; 990 } 991 992 error = SetPictureTransform(src, &xf86_crtc->crtc_to_framebuffer); 993 if (error) { 994 ErrorF("SetPictureTransform failed for transformed scanout " 995 "update\n"); 996 goto free_dst; 997 } 998 999 if (xf86_crtc->filter) 1000 SetPicturePictFilter(src, xf86_crtc->filter, xf86_crtc->params, 1001 xf86_crtc->nparams); 1002 1003 pScreen->SourceValidate = radeonSourceValidate; 1004 CompositePicture(PictOpSrc, 1005 src, NULL, dst, 1006 extents.x1, extents.y1, 0, 0, extents.x1, 1007 extents.y1, extents.x2 - extents.x1, 1008 extents.y2 - extents.y1); 1009 pScreen->SourceValidate = SourceValidate; 1010 1011 free_dst: 1012 FreePicture(dst, None); 1013 free_src: 1014 FreePicture(src, None); 1015 } else 1016 out: 1017 { 1018 GCPtr gc = GetScratchGC(pDraw->depth, pScreen); 1019 1020 ValidateGC(pDraw, gc); 1021 (*gc->ops->CopyArea)(&src_pix->drawable, pDraw, gc, 1022 xf86_crtc->x + extents.x1, xf86_crtc->y + extents.y1, 1023 extents.x2 - extents.x1, extents.y2 - extents.y1, 1024 extents.x1, extents.y1); 1025 FreeScratchGC(gc); 1026 } 1027 1028 info->accel_state->force = force; 1029 1030 return TRUE; 1031} 1032 1033static void 1034radeon_scanout_update_abort(xf86CrtcPtr crtc, void *event_data) 1035{ 1036 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1037 1038 drmmode_crtc->scanout_update_pending = 0; 1039} 1040 1041static void 1042radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t frame, uint64_t usec, 1043 void *event_data) 1044{ 1045 drmmode_crtc_private_ptr drmmode_crtc = event_data; 1046 ScreenPtr screen = crtc->scrn->pScreen; 1047 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1048 1049 if (crtc->enabled && 1050 !drmmode_crtc->flip_pending && 1051 drmmode_crtc->dpms_mode == DPMSModeOn) { 1052 if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id, 1053 screen->GetWindowPixmap(screen->root), 1054 region->extents)) { 1055 radeon_cs_flush_indirect(crtc->scrn); 1056 RegionEmpty(region); 1057 } 1058 } 1059 1060 radeon_scanout_update_abort(crtc, event_data); 1061} 1062 1063static void 1064radeon_scanout_update(xf86CrtcPtr xf86_crtc) 1065{ 1066 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1067 ScrnInfoPtr scrn = xf86_crtc->scrn; 1068 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1069 uintptr_t drm_queue_seq; 1070 DamagePtr pDamage; 1071 RegionPtr pRegion; 1072 BoxRec extents; 1073 1074 if (!xf86_crtc->enabled || 1075 drmmode_crtc->scanout_update_pending || 1076 drmmode_crtc->flip_pending || 1077 drmmode_crtc->dpms_mode != DPMSModeOn) 1078 return; 1079 1080 pDamage = drmmode_crtc->scanout_damage; 1081 if (!pDamage) 1082 return; 1083 1084 pRegion = DamageRegion(pDamage); 1085 if (!RegionNotEmpty(pRegion)) 1086 return; 1087 1088 extents = *RegionExtents(pRegion); 1089 if (!radeon_scanout_extents_intersect(xf86_crtc, &extents)) { 1090 RegionEmpty(pRegion); 1091 return; 1092 } 1093 1094 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1095 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1096 RADEON_DRM_QUEUE_ID_DEFAULT, 1097 drmmode_crtc, 1098 radeon_scanout_update_handler, 1099 radeon_scanout_update_abort, 1100 FALSE); 1101 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1102 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1103 "radeon_drm_queue_alloc failed for scanout update\n"); 1104 radeon_scanout_update_handler(xf86_crtc, 0, 0, drmmode_crtc); 1105 return; 1106 } 1107 1108 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1109 1110 if (!drmmode_wait_vblank(xf86_crtc, DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT, 1111 1, drm_queue_seq, NULL, NULL)) { 1112 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_VBLANK_FAILED)) { 1113 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1114 "drmmode_wait_vblank failed for scanout update: %s\n", 1115 strerror(errno)); 1116 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_VBLANK_FAILED; 1117 } 1118 1119 drmmode_crtc->drmmode->event_context.vblank_handler(pRADEONEnt->fd, 1120 0, 0, 0, 1121 (void*)drm_queue_seq); 1122 drmmode_crtc->wait_flip_nesting_level++; 1123 radeon_drm_queue_handle_deferred(xf86_crtc); 1124 return; 1125 } 1126 1127 if (drmmode_crtc->scanout_status == 1128 (DRMMODE_SCANOUT_FLIP_FAILED | DRMMODE_SCANOUT_VBLANK_FAILED)) { 1129 /* The page flip and vblank ioctls failed before, but the vblank 1130 * ioctl is working again, so we can try re-enabling TearFree 1131 */ 1132 xf86_crtc->funcs->set_mode_major(xf86_crtc, &xf86_crtc->mode, 1133 xf86_crtc->rotation, 1134 xf86_crtc->x, xf86_crtc->y); 1135 } 1136 1137 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_VBLANK_FAILED; 1138} 1139 1140static void 1141radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info, 1142 xf86CrtcPtr xf86_crtc) 1143{ 1144 drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private; 1145 RegionPtr region = DamageRegion(drmmode_crtc->scanout_damage); 1146 ScrnInfoPtr scrn = xf86_crtc->scrn; 1147 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 1148 uintptr_t drm_queue_seq; 1149 unsigned scanout_id; 1150 struct drmmode_fb *fb; 1151 1152 if (drmmode_crtc->scanout_update_pending || 1153 drmmode_crtc->flip_pending || 1154 drmmode_crtc->dpms_mode != DPMSModeOn) 1155 return; 1156 1157 scanout_id = drmmode_crtc->scanout_id ^ 1; 1158 if (!radeon_scanout_do_update(xf86_crtc, scanout_id, 1159 pScreen->GetWindowPixmap(pScreen->root), 1160 region->extents)) 1161 return; 1162 1163 radeon_cs_flush_indirect(scrn); 1164 RegionEmpty(region); 1165 1166 fb = radeon_pixmap_get_fb(drmmode_crtc->scanout[scanout_id].pixmap); 1167 if (!fb) { 1168 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1169 "Failed to get FB for scanout flip.\n"); 1170 return; 1171 } 1172 1173 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc, 1174 RADEON_DRM_QUEUE_CLIENT_DEFAULT, 1175 RADEON_DRM_QUEUE_ID_DEFAULT, fb, 1176 radeon_scanout_flip_handler, 1177 radeon_scanout_flip_abort, TRUE); 1178 if (drm_queue_seq == RADEON_DRM_QUEUE_ERROR) { 1179 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1180 "Allocating DRM event queue entry failed.\n"); 1181 return; 1182 } 1183 1184 if (drmmode_page_flip_target_relative(pRADEONEnt, drmmode_crtc, 1185 fb->handle, 0, drm_queue_seq, 1) 1186 != 0) { 1187 if (!(drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED)) { 1188 xf86DrvMsg(scrn->scrnIndex, X_WARNING, 1189 "flip queue failed in %s: %s, TearFree inactive\n", 1190 __func__, strerror(errno)); 1191 drmmode_crtc->scanout_status |= DRMMODE_SCANOUT_FLIP_FAILED; 1192 } 1193 1194 radeon_drm_abort_entry(drm_queue_seq); 1195 RegionCopy(DamageRegion(drmmode_crtc->scanout_damage), 1196 &drmmode_crtc->scanout_last_region); 1197 RegionEmpty(&drmmode_crtc->scanout_last_region); 1198 radeon_scanout_update(xf86_crtc); 1199 drmmode_crtc_scanout_destroy(drmmode_crtc->drmmode, 1200 &drmmode_crtc->scanout[scanout_id]); 1201 drmmode_crtc->tear_free = FALSE; 1202 return; 1203 } 1204 1205 if (drmmode_crtc->scanout_status & DRMMODE_SCANOUT_FLIP_FAILED) { 1206 xf86DrvMsg(scrn->scrnIndex, X_INFO, "TearFree active again\n"); 1207 drmmode_crtc->scanout_status &= ~DRMMODE_SCANOUT_FLIP_FAILED; 1208 } 1209 1210 drmmode_crtc->scanout_id = scanout_id; 1211 drmmode_crtc->scanout_update_pending = drm_queue_seq; 1212 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->flip_pending, fb); 1213} 1214 1215static void RADEONBlockHandler_KMS(BLOCKHANDLER_ARGS_DECL) 1216{ 1217 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1218 RADEONInfoPtr info = RADEONPTR(pScrn); 1219 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1220 int c; 1221 1222 pScreen->BlockHandler = info->BlockHandler; 1223 (*pScreen->BlockHandler) (BLOCKHANDLER_ARGS); 1224 pScreen->BlockHandler = RADEONBlockHandler_KMS; 1225 1226 if (!xf86ScreenToScrn(radeon_primary_screen(pScreen))->vtSema) 1227 return; 1228 1229 if (!pScreen->isGPU) 1230 { 1231 for (c = 0; c < xf86_config->num_crtc; c++) { 1232 xf86CrtcPtr crtc = xf86_config->crtc[c]; 1233 drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private; 1234 1235 if (drmmode_crtc->rotate.pixmap) 1236 continue; 1237 1238 if (drmmode_crtc->tear_free) 1239 radeon_scanout_flip(pScreen, info, crtc); 1240 else if (drmmode_crtc->scanout[drmmode_crtc->scanout_id].pixmap) 1241 radeon_scanout_update(crtc); 1242 } 1243 } 1244 1245 radeon_cs_flush_indirect(pScrn); 1246 1247 radeon_dirty_update(pScrn); 1248} 1249 1250static Bool RADEONIsFastFBWorking(ScrnInfoPtr pScrn) 1251{ 1252 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1253 struct drm_radeon_info ginfo; 1254 int r; 1255 uint32_t tmp = 0; 1256 1257 memset(&ginfo, 0, sizeof(ginfo)); 1258 ginfo.request = RADEON_INFO_FASTFB_WORKING; 1259 ginfo.value = (uintptr_t)&tmp; 1260 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1261 if (r) { 1262 return FALSE; 1263 } 1264 if (tmp == 1) 1265 return TRUE; 1266 return FALSE; 1267} 1268 1269static Bool RADEONIsFusionGARTWorking(ScrnInfoPtr pScrn) 1270{ 1271 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1272 struct drm_radeon_info ginfo; 1273 int r; 1274 uint32_t tmp; 1275 1276 memset(&ginfo, 0, sizeof(ginfo)); 1277 ginfo.request = RADEON_INFO_FUSION_GART_WORKING; 1278 ginfo.value = (uintptr_t)&tmp; 1279 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1280 if (r) { 1281 return FALSE; 1282 } 1283 if (tmp == 1) 1284 return TRUE; 1285 return FALSE; 1286} 1287 1288static Bool RADEONIsAccelWorking(ScrnInfoPtr pScrn) 1289{ 1290 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1291 RADEONInfoPtr info = RADEONPTR(pScrn); 1292 struct drm_radeon_info ginfo; 1293 int r; 1294 uint32_t tmp; 1295 1296 memset(&ginfo, 0, sizeof(ginfo)); 1297 if (info->dri2.pKernelDRMVersion->version_minor >= 5) 1298 ginfo.request = RADEON_INFO_ACCEL_WORKING2; 1299 else 1300 ginfo.request = RADEON_INFO_ACCEL_WORKING; 1301 ginfo.value = (uintptr_t)&tmp; 1302 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1303 if (r) { 1304 /* If kernel is too old before 2.6.32 than assume accel is working */ 1305 if (r == -EINVAL) { 1306 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Kernel too old missing accel " 1307 "information, assuming accel is working\n"); 1308 return TRUE; 1309 } 1310 return FALSE; 1311 } 1312 if (info->ChipFamily == CHIP_FAMILY_HAWAII) { 1313 if (tmp == 2 || tmp == 3) 1314 return TRUE; 1315 } else if (tmp) { 1316 return TRUE; 1317 } 1318 return FALSE; 1319} 1320 1321/* This is called by RADEONPreInit to set up the default visual */ 1322static Bool RADEONPreInitVisual(ScrnInfoPtr pScrn) 1323{ 1324 RADEONInfoPtr info = RADEONPTR(pScrn); 1325 1326 if (!xf86SetDepthBpp(pScrn, 0, 0, 0, Support32bppFb)) 1327 return FALSE; 1328 1329 switch (pScrn->depth) { 1330 case 8: 1331 case 15: 1332 case 16: 1333 case 24: 1334 case 30: 1335 break; 1336 1337 default: 1338 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1339 "Given depth (%d) is not supported by %s driver\n", 1340 pScrn->depth, RADEON_DRIVER_NAME); 1341 return FALSE; 1342 } 1343 1344 xf86PrintDepthBpp(pScrn); 1345 1346 info->pix24bpp = xf86GetBppFromDepth(pScrn, 1347 pScrn->depth); 1348 info->pixel_bytes = pScrn->bitsPerPixel / 8; 1349 1350 if (info->pix24bpp == 24) { 1351 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1352 "Radeon does NOT support 24bpp\n"); 1353 return FALSE; 1354 } 1355 1356 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1357 "Pixel depth = %d bits stored in %d byte%s (%d bpp pixmaps)\n", 1358 pScrn->depth, 1359 info->pixel_bytes, 1360 info->pixel_bytes > 1 ? "s" : "", 1361 info->pix24bpp); 1362 1363 if (!xf86SetDefaultVisual(pScrn, -1)) return FALSE; 1364 1365 if (pScrn->depth > 8 && pScrn->defaultVisual != TrueColor) { 1366 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1367 "Default visual (%s) is not supported at depth %d\n", 1368 xf86GetVisualName(pScrn->defaultVisual), pScrn->depth); 1369 return FALSE; 1370 } 1371 return TRUE; 1372} 1373 1374/* This is called by RADEONPreInit to handle all color weight issues */ 1375static Bool RADEONPreInitWeight(ScrnInfoPtr pScrn) 1376{ 1377 RADEONInfoPtr info = RADEONPTR(pScrn); 1378 1379 /* Save flag for 6 bit DAC to use for 1380 setting CRTC registers. Otherwise use 1381 an 8 bit DAC, even if xf86SetWeight sets 1382 pScrn->rgbBits to some value other than 1383 8. */ 1384 info->dac6bits = FALSE; 1385 1386 if (pScrn->depth > 8) { 1387 rgb defaultWeight = { 0, 0, 0 }; 1388 1389 if (!xf86SetWeight(pScrn, defaultWeight, defaultWeight)) return FALSE; 1390 } else { 1391 pScrn->rgbBits = 8; 1392 } 1393 1394 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1395 "Using %d bits per RGB (%d bit DAC)\n", 1396 pScrn->rgbBits, info->dac6bits ? 6 : 8); 1397 1398 return TRUE; 1399} 1400 1401static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn) 1402{ 1403 RADEONInfoPtr info = RADEONPTR(pScrn); 1404 1405 if (!(info->accel_state = calloc(1, sizeof(struct radeon_accel_state)))) { 1406 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Unable to allocate accel_state rec!\n"); 1407 return FALSE; 1408 } 1409 1410 /* Check whether direct mapping is used for fast fb access*/ 1411 if (RADEONIsFastFBWorking(pScrn)) { 1412 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct mapping of fb aperture is enabled for fast fb access.\n"); 1413 info->is_fast_fb = TRUE; 1414 } 1415 1416 if (!xf86ReturnOptValBool(info->Options, OPTION_ACCEL, TRUE) || 1417 (!RADEONIsAccelWorking(pScrn))) { 1418 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1419 "GPU accel disabled or not working, using shadowfb for KMS\n"); 1420shadowfb: 1421 if (!xf86LoadSubModule(pScrn, "shadow")) 1422 return FALSE; 1423 1424 info->r600_shadow_fb = TRUE; 1425 return TRUE; 1426 } 1427 1428#ifdef DRI2 1429 info->dri2.available = !!xf86LoadSubModule(pScrn, "dri2"); 1430#endif 1431 1432 if (radeon_glamor_pre_init(pScrn)) 1433 return TRUE; 1434 1435 if (info->ChipFamily >= CHIP_FAMILY_TAHITI) { 1436 goto shadowfb; 1437 } else if (info->ChipFamily == CHIP_FAMILY_PALM) { 1438 info->accel_state->allowHWDFS = RADEONIsFusionGARTWorking(pScrn); 1439 } else 1440 info->accel_state->allowHWDFS = TRUE; 1441 1442 if ((info->ChipFamily == CHIP_FAMILY_RS100) || 1443 (info->ChipFamily == CHIP_FAMILY_RS200) || 1444 (info->ChipFamily == CHIP_FAMILY_RS300) || 1445 (info->ChipFamily == CHIP_FAMILY_RS400) || 1446 (info->ChipFamily == CHIP_FAMILY_RS480) || 1447 (info->ChipFamily == CHIP_FAMILY_RS600) || 1448 (info->ChipFamily == CHIP_FAMILY_RS690) || 1449 (info->ChipFamily == CHIP_FAMILY_RS740)) 1450 info->accel_state->has_tcl = FALSE; 1451 else { 1452 info->accel_state->has_tcl = TRUE; 1453 } 1454 1455 { 1456 int errmaj = 0, errmin = 0; 1457 info->exaReq.majorversion = EXA_VERSION_MAJOR; 1458 info->exaReq.minorversion = EXA_VERSION_MINOR; 1459 if (!LoadSubModule(pScrn->module, "exa", NULL, NULL, NULL, 1460 &info->exaReq, &errmaj, &errmin)) { 1461 LoaderErrorMsg(NULL, "exa", errmaj, errmin); 1462 return FALSE; 1463 } 1464 } 1465 1466 return TRUE; 1467} 1468 1469static Bool RADEONPreInitChipType_KMS(ScrnInfoPtr pScrn) 1470{ 1471 RADEONInfoPtr info = RADEONPTR(pScrn); 1472 int i; 1473 1474 info->Chipset = PCI_DEV_DEVICE_ID(info->PciInfo); 1475 pScrn->chipset = (char *)xf86TokenToString(RADEONChipsets, info->Chipset); 1476 if (!pScrn->chipset) { 1477 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1478 "ChipID 0x%04x is not recognized\n", info->Chipset); 1479 return FALSE; 1480 } 1481 1482 if (info->Chipset < 0) { 1483 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1484 "Chipset \"%s\" is not recognized\n", pScrn->chipset); 1485 return FALSE; 1486 } 1487 xf86DrvMsg(pScrn->scrnIndex, X_PROBED, 1488 "Chipset: \"%s\" (ChipID = 0x%04x)\n", 1489 pScrn->chipset, 1490 info->Chipset); 1491 1492 for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) { 1493 if (info->Chipset == RADEONCards[i].pci_device_id) { 1494 RADEONCardInfo *card = &RADEONCards[i]; 1495 info->ChipFamily = card->chip_family; 1496 break; 1497 } 1498 } 1499 1500#ifdef RENDER 1501 info->RenderAccel = xf86ReturnOptValBool(info->Options, OPTION_RENDER_ACCEL, 1502 info->Chipset != PCI_CHIP_RN50_515E && 1503 info->Chipset != PCI_CHIP_RN50_5969); 1504#endif 1505 return TRUE; 1506} 1507 1508static int radeon_get_drm_master_fd(ScrnInfoPtr pScrn) 1509{ 1510 RADEONInfoPtr info = RADEONPTR(pScrn); 1511#ifdef XF86_PDEV_SERVER_FD 1512 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1513#endif 1514 struct pci_device *dev = info->PciInfo; 1515 char *busid; 1516 int fd; 1517 1518#ifdef XF86_PDEV_SERVER_FD 1519 if (pRADEONEnt->platform_dev) { 1520 fd = xf86_get_platform_device_int_attrib(pRADEONEnt->platform_dev, 1521 ODEV_ATTRIB_FD, -1); 1522 if (fd != -1) 1523 return fd; 1524 } 1525#endif 1526 1527 XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d", 1528 dev->domain, dev->bus, dev->dev, dev->func); 1529 1530 fd = drmOpen(NULL, busid); 1531 if (fd == -1) 1532 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1533 "[drm] Failed to open DRM device for %s: %s\n", 1534 busid, strerror(errno)); 1535 1536 free(busid); 1537 return fd; 1538} 1539 1540static Bool radeon_open_drm_master(ScrnInfoPtr pScrn) 1541{ 1542 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1543 drmSetVersion sv; 1544 int err; 1545 1546 if (pRADEONEnt->fd) { 1547 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1548 " reusing fd for second head\n"); 1549 pRADEONEnt->fd_ref++; 1550 return TRUE; 1551 } 1552 1553 pRADEONEnt->fd = radeon_get_drm_master_fd(pScrn); 1554 if (pRADEONEnt->fd == -1) 1555 return FALSE; 1556 1557 /* Check that what we opened was a master or a master-capable FD, 1558 * by setting the version of the interface we'll use to talk to it. 1559 * (see DRIOpenDRMMaster() in DRI1) 1560 */ 1561 sv.drm_di_major = 1; 1562 sv.drm_di_minor = 1; 1563 sv.drm_dd_major = -1; 1564 sv.drm_dd_minor = -1; 1565 err = drmSetInterfaceVersion(pRADEONEnt->fd, &sv); 1566 if (err != 0) { 1567 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1568 "[drm] failed to set drm interface version.\n"); 1569 drmClose(pRADEONEnt->fd); 1570 pRADEONEnt->fd = -1; 1571 1572 return FALSE; 1573 } 1574 1575 pRADEONEnt->fd_ref = 1; 1576 return TRUE; 1577} 1578 1579static Bool r600_get_tile_config(ScrnInfoPtr pScrn) 1580{ 1581 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1582 RADEONInfoPtr info = RADEONPTR(pScrn); 1583 struct drm_radeon_info ginfo; 1584 int r; 1585 uint32_t tmp; 1586 1587 if (info->ChipFamily < CHIP_FAMILY_R600) 1588 return FALSE; 1589 1590 memset(&ginfo, 0, sizeof(ginfo)); 1591 ginfo.request = RADEON_INFO_TILING_CONFIG; 1592 ginfo.value = (uintptr_t)&tmp; 1593 r = drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_INFO, &ginfo, sizeof(ginfo)); 1594 if (r) 1595 return FALSE; 1596 1597 info->tile_config = tmp; 1598 info->r7xx_bank_op = 0; 1599 if (info->ChipFamily >= CHIP_FAMILY_CEDAR) { 1600 if (info->dri2.pKernelDRMVersion->version_minor >= 7) { 1601 switch (info->tile_config & 0xf) { 1602 case 0: 1603 info->num_channels = 1; 1604 break; 1605 case 1: 1606 info->num_channels = 2; 1607 break; 1608 case 2: 1609 info->num_channels = 4; 1610 break; 1611 case 3: 1612 info->num_channels = 8; 1613 break; 1614 default: 1615 return FALSE; 1616 } 1617 1618 switch((info->tile_config & 0xf0) >> 4) { 1619 case 0: 1620 info->num_banks = 4; 1621 break; 1622 case 1: 1623 info->num_banks = 8; 1624 break; 1625 case 2: 1626 info->num_banks = 16; 1627 break; 1628 default: 1629 return FALSE; 1630 } 1631 1632 switch ((info->tile_config & 0xf00) >> 8) { 1633 case 0: 1634 info->group_bytes = 256; 1635 break; 1636 case 1: 1637 info->group_bytes = 512; 1638 break; 1639 default: 1640 return FALSE; 1641 } 1642 } else 1643 return FALSE; 1644 } else { 1645 switch((info->tile_config & 0xe) >> 1) { 1646 case 0: 1647 info->num_channels = 1; 1648 break; 1649 case 1: 1650 info->num_channels = 2; 1651 break; 1652 case 2: 1653 info->num_channels = 4; 1654 break; 1655 case 3: 1656 info->num_channels = 8; 1657 break; 1658 default: 1659 return FALSE; 1660 } 1661 switch((info->tile_config & 0x30) >> 4) { 1662 case 0: 1663 info->num_banks = 4; 1664 break; 1665 case 1: 1666 info->num_banks = 8; 1667 break; 1668 default: 1669 return FALSE; 1670 } 1671 switch((info->tile_config & 0xc0) >> 6) { 1672 case 0: 1673 info->group_bytes = 256; 1674 break; 1675 case 1: 1676 info->group_bytes = 512; 1677 break; 1678 default: 1679 return FALSE; 1680 } 1681 } 1682 1683 info->have_tiling_info = TRUE; 1684 return TRUE; 1685} 1686 1687static void RADEONSetupCapabilities(ScrnInfoPtr pScrn) 1688{ 1689 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 1690 RADEONInfoPtr info = RADEONPTR(pScrn); 1691 uint64_t value; 1692 int ret; 1693 1694 pScrn->capabilities = 0; 1695 1696 /* PRIME offloading requires acceleration */ 1697 if (info->r600_shadow_fb) 1698 return; 1699 1700 ret = drmGetCap(pRADEONEnt->fd, DRM_CAP_PRIME, &value); 1701 if (ret == 0) { 1702 if (value & DRM_PRIME_CAP_EXPORT) 1703 pScrn->capabilities |= RR_Capability_SourceOutput | RR_Capability_SourceOffload; 1704 if (value & DRM_PRIME_CAP_IMPORT) { 1705 pScrn->capabilities |= RR_Capability_SinkOffload; 1706 if (info->drmmode.count_crtcs) 1707 pScrn->capabilities |= RR_Capability_SinkOutput; 1708 } 1709 } 1710} 1711 1712/* When the root window is created, initialize the screen contents from 1713 * console if -background none was specified on the command line 1714 */ 1715static Bool RADEONCreateWindow_oneshot(WindowPtr pWin) 1716{ 1717 ScreenPtr pScreen = pWin->drawable.pScreen; 1718 ScrnInfoPtr pScrn; 1719 RADEONInfoPtr info; 1720 Bool ret; 1721 1722 if (pWin != pScreen->root) 1723 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1724 1725 pScrn = xf86ScreenToScrn(pScreen); 1726 info = RADEONPTR(pScrn); 1727 pScreen->CreateWindow = info->CreateWindow; 1728 ret = pScreen->CreateWindow(pWin); 1729 1730 if (ret) 1731 drmmode_copy_fb(pScrn, &info->drmmode); 1732 1733 return ret; 1734} 1735 1736/* When the root window is mapped, set the initial modes */ 1737void RADEONWindowExposures_oneshot(WindowPtr pWin, RegionPtr pRegion 1738#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1739 , RegionPtr pBSRegion 1740#endif 1741 ) 1742{ 1743 ScreenPtr pScreen = pWin->drawable.pScreen; 1744 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 1745 RADEONInfoPtr info = RADEONPTR(pScrn); 1746 1747 if (pWin != pScreen->root) 1748 ErrorF("%s called for non-root window %p\n", __func__, pWin); 1749 1750 pScreen->WindowExposures = info->WindowExposures; 1751#if XORG_VERSION_CURRENT < XORG_VERSION_NUMERIC(1,16,99,901,0) 1752 pScreen->WindowExposures(pWin, pRegion, pBSRegion); 1753#else 1754 pScreen->WindowExposures(pWin, pRegion); 1755#endif 1756 1757 radeon_finish(pScrn, info->front_buffer); 1758 drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE); 1759} 1760 1761Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags) 1762{ 1763 RADEONInfoPtr info; 1764 RADEONEntPtr pRADEONEnt; 1765 MessageType from; 1766 Gamma zeros = { 0.0, 0.0, 0.0 }; 1767 uint32_t tiling = 0; 1768 int cpp; 1769 1770 if (flags & PROBE_DETECT) 1771 return TRUE; 1772 1773 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 1774 "RADEONPreInit_KMS\n"); 1775 if (pScrn->numEntities != 1) return FALSE; 1776 1777 pRADEONEnt = xf86GetEntityPrivate(pScrn->entityList[0], 1778 getRADEONEntityIndex())->ptr; 1779 if (pRADEONEnt->num_scrns == ARRAY_SIZE(pRADEONEnt->scrn)) { 1780 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1781 "Only up to %u Zaphod instances supported\n", 1782 (unsigned)ARRAY_SIZE(pRADEONEnt->scrn)); 1783 return FALSE; 1784 } 1785 1786 if (!RADEONGetRec(pScrn)) return FALSE; 1787 1788 info = RADEONPTR(pScrn); 1789 1790 info->instance_id = pRADEONEnt->num_scrns++; 1791 pRADEONEnt->scrn[info->instance_id] = pScrn; 1792 1793 info->pEnt = xf86GetEntityInfo(pScrn->entityList[pScrn->numEntities - 1]); 1794 if (info->pEnt->location.type != BUS_PCI 1795#ifdef XSERVER_PLATFORM_BUS 1796 && info->pEnt->location.type != BUS_PLATFORM 1797#endif 1798 ) 1799 return FALSE; 1800 1801 if (xf86IsEntityShared(pScrn->entityList[0]) && 1802 info->instance_id == 0) { 1803 xf86SetPrimInitDone(pScrn->entityList[0]); 1804 } 1805 1806 info->PciInfo = xf86GetPciInfoForEntity(info->pEnt->index); 1807 pScrn->monitor = pScrn->confScreen->monitor; 1808 1809 if (!RADEONPreInitVisual(pScrn)) 1810 return FALSE; 1811 1812 xf86CollectOptions(pScrn, NULL); 1813 if (!(info->Options = malloc(sizeof(RADEONOptions_KMS)))) 1814 return FALSE; 1815 1816 memcpy(info->Options, RADEONOptions_KMS, sizeof(RADEONOptions_KMS)); 1817 xf86ProcessOptions(pScrn->scrnIndex, pScrn->options, info->Options); 1818 1819 if (!RADEONPreInitWeight(pScrn)) 1820 return FALSE; 1821 1822 if (!RADEONPreInitChipType_KMS(pScrn)) 1823 return FALSE; 1824 1825 if (radeon_open_drm_master(pScrn) == FALSE) { 1826 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1827 return FALSE; 1828 } 1829 1830 info->dri2.available = FALSE; 1831 info->dri2.enabled = FALSE; 1832 info->dri2.pKernelDRMVersion = drmGetVersion(pRADEONEnt->fd); 1833 if (!info->dri2.pKernelDRMVersion) { 1834 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1835 "RADEONDRIGetVersion failed to get the DRM version\n"); 1836 return FALSE; 1837 } 1838 1839 /* Get ScreenInit function */ 1840 if (!xf86LoadSubModule(pScrn, "fb")) 1841 return FALSE; 1842 1843 if (!RADEONPreInitAccel_KMS(pScrn)) 1844 return FALSE; 1845 1846 /* Depth 30 only supported since Linux 3.16 / kms driver minor version 39 */ 1847 if (pScrn->depth == 30 && info->dri2.pKernelDRMVersion->version_minor < 39) { 1848 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 1849 "Depth 30 is not supported. Kernel too old. Needs Linux 3.16+\n"); 1850 return FALSE; 1851 } 1852 1853 radeon_drm_queue_init(pScrn); 1854 1855 info->allowColorTiling2D = FALSE; 1856 1857 /* don't enable tiling if accel is not enabled */ 1858 if (!info->r600_shadow_fb) { 1859 Bool colorTilingDefault = 1860 info->ChipFamily >= CHIP_FAMILY_R300 && 1861 /* this check could be removed sometime after a big mesa release 1862 * with proper bit, in the meantime you need to set tiling option in 1863 * xorg configuration files 1864 */ 1865 info->ChipFamily <= CHIP_FAMILY_MULLINS && 1866 !info->is_fast_fb; 1867 1868 /* 2D color tiling */ 1869 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1870 info->allowColorTiling2D = xf86ReturnOptValBool(info->Options, OPTION_COLOR_TILING_2D, 1871 info->ChipFamily <= CHIP_FAMILY_MULLINS); 1872 } 1873 1874 if (info->ChipFamily >= CHIP_FAMILY_R600) { 1875 /* set default group bytes, overridden by kernel info below */ 1876 info->group_bytes = 256; 1877 info->have_tiling_info = FALSE; 1878 if (info->dri2.pKernelDRMVersion->version_minor >= 6) { 1879 if (r600_get_tile_config(pScrn)) { 1880 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1881 OPTION_COLOR_TILING, colorTilingDefault); 1882 if (!info->use_glamor) { 1883 /* need working DFS for tiling */ 1884 if (info->ChipFamily == CHIP_FAMILY_PALM && 1885 !info->accel_state->allowHWDFS) 1886 info->allowColorTiling = FALSE; 1887 } 1888 } else 1889 info->allowColorTiling = FALSE; 1890 } else 1891 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1892 "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or newer\n"); 1893 } else 1894 info->allowColorTiling = xf86ReturnOptValBool(info->Options, 1895 OPTION_COLOR_TILING, colorTilingDefault); 1896 } else 1897 info->allowColorTiling = FALSE; 1898 1899 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1900 "KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis"); 1901 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1902 "KMS Color Tiling 2D: %sabled\n", info->allowColorTiling2D ? "en" : "dis"); 1903 1904#if USE_GLAMOR 1905 if (info->use_glamor) { 1906 info->shadow_primary = xf86ReturnOptValBool(info->Options, 1907 OPTION_SHADOW_PRIMARY, FALSE); 1908 1909 if (info->shadow_primary) 1910 xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ShadowPrimary enabled\n"); 1911 } 1912#endif 1913 1914 if (!info->r600_shadow_fb) { 1915 from = X_DEFAULT; 1916 1917 info->tear_free = 2; 1918 if (xf86GetOptValBool(info->Options, OPTION_TEAR_FREE, 1919 &info->tear_free)) 1920 from = X_CONFIG; 1921 xf86DrvMsg(pScrn->scrnIndex, from, "TearFree property default: %s\n", 1922 info->tear_free == 2 ? "auto" : (info->tear_free ? "on" : "off")); 1923 } 1924 1925 if (!pScrn->is_gpu) { 1926 if (info->dri2.pKernelDRMVersion->version_minor >= 8) { 1927 info->allowPageFlip = xf86ReturnOptValBool(info->Options, 1928 OPTION_PAGE_FLIP, TRUE); 1929 1930 if (info->shadow_primary) { 1931 xf86DrvMsg(pScrn->scrnIndex, 1932 info->allowPageFlip ? X_WARNING : X_DEFAULT, 1933 "KMS Pageflipping: disabled%s\n", 1934 info->allowPageFlip ? 1935 " because of ShadowPrimary" : ""); 1936 info->allowPageFlip = FALSE; 1937 } else { 1938 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1939 "KMS Pageflipping: %sabled\n", 1940 info->allowPageFlip ? "en" : "dis"); 1941 } 1942 } 1943 1944 if (!info->use_glamor) { 1945 info->swapBuffersWait = 1946 xf86ReturnOptValBool(info->Options, OPTION_SWAPBUFFERS_WAIT, TRUE); 1947 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 1948 "SwapBuffers wait for vsync: %sabled\n", 1949 info->swapBuffersWait ? "en" : "dis"); 1950 } 1951 } 1952 1953 if (xf86ReturnOptValBool(info->Options, OPTION_DELETE_DP12, FALSE)) { 1954 info->drmmode.delete_dp_12_displays = TRUE; 1955 } 1956 1957 if (drmmode_pre_init(pScrn, &info->drmmode, pScrn->bitsPerPixel / 8) == FALSE) { 1958 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Kernel modesetting setup failed\n"); 1959 return FALSE; 1960 } 1961 1962 RADEONSetupCapabilities(pScrn); 1963 1964 if (info->drmmode.count_crtcs == 1) 1965 pRADEONEnt->HasCRTC2 = FALSE; 1966 else 1967 pRADEONEnt->HasCRTC2 = TRUE; 1968 1969 1970 /* fix up cloning on rn50 cards 1971 * since they only have one crtc sometimes the xserver doesn't assign 1972 * a crtc to one of the outputs even though both outputs have common modes 1973 * which results in only one monitor being enabled. Assign a crtc here so 1974 * that both outputs light up. 1975 */ 1976 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 1977 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 1978 int i; 1979 1980 for (i = 0; i < xf86_config->num_output; i++) { 1981 xf86OutputPtr output = xf86_config->output[i]; 1982 1983 /* XXX: double check crtc mode */ 1984 if (output->probed_modes && !output->crtc) 1985 output->crtc = xf86_config->crtc[0]; 1986 } 1987 } 1988 1989 /* set cursor size */ 1990 if (info->ChipFamily >= CHIP_FAMILY_BONAIRE) { 1991 info->cursor_w = CURSOR_WIDTH_CIK; 1992 info->cursor_h = CURSOR_HEIGHT_CIK; 1993 } else { 1994 info->cursor_w = CURSOR_WIDTH; 1995 info->cursor_h = CURSOR_HEIGHT; 1996 } 1997 1998 { 1999 struct drm_radeon_gem_info mminfo; 2000 2001 if (!drmCommandWriteRead(pRADEONEnt->fd, DRM_RADEON_GEM_INFO, &mminfo, sizeof(mminfo))) 2002 { 2003 info->vram_size = mminfo.vram_visible; 2004 info->gart_size = mminfo.gart_size; 2005 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2006 "mem size init: gart size :%llx vram size: s:%llx visible:%llx\n", 2007 (unsigned long long)mminfo.gart_size, 2008 (unsigned long long)mminfo.vram_size, 2009 (unsigned long long)mminfo.vram_visible); 2010 } 2011 } 2012 2013 if (!info->use_glamor) { 2014 info->exa_pixmaps = xf86ReturnOptValBool(info->Options, 2015 OPTION_EXA_PIXMAPS, 2016 (info->vram_size > (32 * 1024 * 1024) && 2017 info->RenderAccel && 2018 !info->is_fast_fb)); 2019 if (info->exa_pixmaps) 2020 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2021 "EXA: Driver will allow EXA pixmaps in VRAM\n"); 2022 else 2023 xf86DrvMsg(pScrn->scrnIndex, X_INFO, 2024 "EXA: Driver will not allow EXA pixmaps in VRAM\n"); 2025 } 2026 2027 /* no tiled scanout on r6xx+ yet */ 2028 if (info->allowColorTiling) { 2029 if (info->ChipFamily >= CHIP_FAMILY_R600) 2030 tiling |= RADEON_TILING_MICRO; 2031 else 2032 tiling |= RADEON_TILING_MACRO; 2033 } 2034 cpp = pScrn->bitsPerPixel / 8; 2035 pScrn->displayWidth = 2036 RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling)); 2037 2038 /* Set display resolution */ 2039 xf86SetDpi(pScrn, 0, 0); 2040 2041 if (!xf86SetGamma(pScrn, zeros)) return FALSE; 2042 2043 if (!xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) { 2044 if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE; 2045 } 2046 2047 if (!pScrn->modes 2048#ifdef XSERVER_PLATFORM_BUS 2049 && !pScrn->is_gpu 2050#endif 2051 ) { 2052 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n"); 2053 return FALSE; 2054 } 2055 2056 return TRUE; 2057} 2058 2059static Bool RADEONCursorInit_KMS(ScreenPtr pScreen) 2060{ 2061 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2062 RADEONInfoPtr info = RADEONPTR(pScrn); 2063 2064 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2065 "Initializing Cursor\n"); 2066 2067 /* Set Silken Mouse */ 2068 xf86SetSilkenMouse(pScreen); 2069 2070 /* Cursor setup */ 2071 miDCInitialize(pScreen, xf86GetPointerScreenFuncs()); 2072 2073 if (info->allowPageFlip) { 2074 miPointerScreenPtr PointPriv = 2075 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2076 2077 if (!dixRegisterScreenPrivateKey(&radeon_device_private_key, pScreen, 2078 PRIVATE_DEVICE, 2079 sizeof(struct radeon_device_priv))) { 2080 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "dixRegisterScreenPrivateKey failed\n"); 2081 return FALSE; 2082 } 2083 2084 info->SpriteFuncs = PointPriv->spriteFuncs; 2085 PointPriv->spriteFuncs = &drmmode_sprite_funcs; 2086 } 2087 2088 if (xf86ReturnOptValBool(info->Options, OPTION_SW_CURSOR, FALSE)) 2089 return TRUE; 2090 2091 if (!xf86_cursors_init(pScreen, info->cursor_w, info->cursor_h, 2092 HARDWARE_CURSOR_TRUECOLOR_AT_8BPP | 2093 HARDWARE_CURSOR_AND_SOURCE_WITH_MASK | 2094 HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_1 | 2095 HARDWARE_CURSOR_UPDATE_UNHIDDEN | 2096 HARDWARE_CURSOR_ARGB)) { 2097 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "xf86_cursors_init failed\n"); 2098 return FALSE; 2099 } 2100 2101 return TRUE; 2102} 2103 2104void 2105RADEONBlank(ScrnInfoPtr pScrn) 2106{ 2107 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2108 xf86OutputPtr output; 2109 xf86CrtcPtr crtc; 2110 int o, c; 2111 2112 for (c = 0; c < xf86_config->num_crtc; c++) { 2113 crtc = xf86_config->crtc[c]; 2114 for (o = 0; o < xf86_config->num_output; o++) { 2115 output = xf86_config->output[o]; 2116 if (output->crtc != crtc) 2117 continue; 2118 2119 output->funcs->dpms(output, DPMSModeOff); 2120 } 2121 crtc->funcs->dpms(crtc, DPMSModeOff); 2122 } 2123} 2124 2125void 2126RADEONUnblank(ScrnInfoPtr pScrn) 2127{ 2128 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2129 xf86OutputPtr output; 2130 xf86CrtcPtr crtc; 2131 int o, c; 2132 for (c = 0; c < xf86_config->num_crtc; c++) { 2133 crtc = xf86_config->crtc[c]; 2134 if(!crtc->enabled) 2135 continue; 2136 crtc->funcs->dpms(crtc, DPMSModeOn); 2137 for (o = 0; o < xf86_config->num_output; o++) { 2138 output = xf86_config->output[o]; 2139 if (output->crtc != crtc) 2140 continue; 2141 output->funcs->dpms(output, DPMSModeOn); 2142 } 2143 } 2144} 2145 2146 2147static Bool RADEONSaveScreen_KMS(ScreenPtr pScreen, int mode) 2148{ 2149 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2150 Bool unblank; 2151 2152 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2153 "RADEONSaveScreen(%d)\n", mode); 2154 2155 unblank = xf86IsUnblank(mode); 2156 if (unblank) SetTimeSinceLastInputEvent(); 2157 2158 if (pScrn && pScrn->vtSema) { 2159 if (unblank) 2160 RADEONUnblank(pScrn); 2161 else 2162 RADEONBlank(pScrn); 2163 } 2164 return TRUE; 2165} 2166 2167static Bool radeon_set_drm_master(ScrnInfoPtr pScrn) 2168{ 2169 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2170 int err; 2171 2172#ifdef XF86_PDEV_SERVER_FD 2173 if (pRADEONEnt->platform_dev && 2174 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2175 return TRUE; 2176#endif 2177 2178 err = drmSetMaster(pRADEONEnt->fd); 2179 if (err) 2180 ErrorF("Unable to retrieve master\n"); 2181 2182 return err == 0; 2183} 2184 2185static void radeon_drop_drm_master(ScrnInfoPtr pScrn) 2186{ 2187 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2188 2189#ifdef XF86_PDEV_SERVER_FD 2190 if (pRADEONEnt->platform_dev && 2191 (pRADEONEnt->platform_dev->flags & XF86_PDEV_SERVER_FD)) 2192 return; 2193#endif 2194 2195 drmDropMaster(pRADEONEnt->fd); 2196} 2197 2198/* Called at the end of each server generation. Restore the original 2199 * text mode, unmap video memory, and unwrap and call the saved 2200 * CloseScreen function. 2201 */ 2202static Bool RADEONCloseScreen_KMS(ScreenPtr pScreen) 2203{ 2204 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2205 RADEONInfoPtr info = RADEONPTR(pScrn); 2206 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2207 2208 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2209 "RADEONCloseScreen\n"); 2210 2211 /* Clear mask of assigned crtc's in this generation */ 2212 pRADEONEnt->assigned_crtcs = 0; 2213 2214 drmmode_uevent_fini(pScrn, &info->drmmode); 2215 radeon_drm_queue_close(pScrn); 2216 radeon_cs_flush_indirect(pScrn); 2217 2218 if (info->callback_event_type != -1) { 2219 DeleteCallback(&EventCallback, radeon_event_callback, pScrn); 2220 DeleteCallback(&FlushCallback, radeon_flush_callback, pScrn); 2221 } 2222 2223 if (info->accel_state->exa) { 2224 exaDriverFini(pScreen); 2225 free(info->accel_state->exa); 2226 info->accel_state->exa = NULL; 2227 } 2228 2229 radeon_sync_close(pScreen); 2230 2231 if (info->accel_state->use_vbos) 2232 radeon_vbo_free_lists(pScrn); 2233 2234 radeon_drop_drm_master(pScrn); 2235 2236 drmmode_fini(pScrn, &info->drmmode); 2237 if (info->dri2.enabled) 2238 radeon_dri2_close_screen(pScreen); 2239 2240 radeon_glamor_fini(pScreen); 2241 2242 pScrn->vtSema = FALSE; 2243 xf86ClearPrimInitDone(info->pEnt->index); 2244 2245 if (info->allowPageFlip) { 2246 miPointerScreenPtr PointPriv = 2247 dixLookupPrivate(&pScreen->devPrivates, miPointerScreenKey); 2248 2249 if (PointPriv->spriteFuncs == &drmmode_sprite_funcs) 2250 PointPriv->spriteFuncs = info->SpriteFuncs; 2251 } 2252 2253 pScreen->BlockHandler = info->BlockHandler; 2254 pScreen->CloseScreen = info->CloseScreen; 2255 return pScreen->CloseScreen(pScreen); 2256} 2257 2258 2259void RADEONFreeScreen_KMS(ScrnInfoPtr pScrn) 2260{ 2261 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2262 "RADEONFreeScreen\n"); 2263 2264 RADEONFreeRec(pScrn); 2265} 2266 2267Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, char **argv) 2268{ 2269 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2270 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2271 RADEONInfoPtr info = RADEONPTR(pScrn); 2272 int subPixelOrder = SubPixelUnknown; 2273 MessageType from; 2274 Bool value; 2275 int driLevel; 2276 const char *s; 2277 void *front_ptr; 2278 2279 pScrn->fbOffset = 0; 2280 2281 miClearVisualTypes(); 2282 if (!miSetVisualTypes(pScrn->depth, 2283 miGetDefaultVisualMask(pScrn->depth), 2284 pScrn->rgbBits, 2285 pScrn->defaultVisual)) return FALSE; 2286 miSetPixmapDepths (); 2287 2288 if (!radeon_set_drm_master(pScrn)) 2289 return FALSE; 2290 2291 info->directRenderingEnabled = FALSE; 2292 if (info->r600_shadow_fb == FALSE) 2293 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen); 2294 2295 if (info->ChipFamily >= CHIP_FAMILY_R600) { 2296 info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd); 2297 2298 if (!info->surf_man) { 2299 xf86DrvMsg(pScreen->myNum, X_ERROR, 2300 "Failed to initialize surface manager\n"); 2301 return FALSE; 2302 } 2303 } 2304 2305 if (!info->bufmgr) 2306 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd); 2307 if (!info->bufmgr) { 2308 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2309 "failed to initialise GEM buffer manager"); 2310 return FALSE; 2311 } 2312 drmmode_set_bufmgr(pScrn, &info->drmmode, info->bufmgr); 2313 2314 if (!info->csm) 2315 info->csm = radeon_cs_manager_gem_ctor(pRADEONEnt->fd); 2316 if (!info->csm) { 2317 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2318 "failed to initialise command submission manager"); 2319 return FALSE; 2320 } 2321 2322 if (!info->cs) 2323 info->cs = radeon_cs_create(info->csm, RADEON_BUFFER_SIZE/4); 2324 if (!info->cs) { 2325 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2326 "failed to initialise command submission buffer"); 2327 return FALSE; 2328 } 2329 2330 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_GTT, info->gart_size); 2331 radeon_cs_space_set_flush(info->cs, (void(*)(void *))radeon_cs_flush_indirect, pScrn); 2332 2333 if (!radeon_setup_kernel_mem(pScreen)) { 2334 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "radeon_setup_kernel_mem failed\n"); 2335 return FALSE; 2336 } 2337 2338 if (!(info->front_buffer->flags & RADEON_BO_FLAGS_GBM)) 2339 front_ptr = info->front_buffer->bo.radeon->ptr; 2340 else 2341 front_ptr = NULL; 2342 2343 if (info->r600_shadow_fb) { 2344 info->fb_shadow = calloc(1, 2345 pScrn->displayWidth * pScrn->virtualY * 2346 ((pScrn->bitsPerPixel + 7) >> 3)); 2347 if (!info->fb_shadow) { 2348 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2349 "Failed to allocate shadow framebuffer\n"); 2350 return FALSE; 2351 } else { 2352 if (!fbScreenInit(pScreen, info->fb_shadow, 2353 pScrn->virtualX, pScrn->virtualY, 2354 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2355 pScrn->bitsPerPixel)) 2356 return FALSE; 2357 } 2358 } 2359 2360 if (info->r600_shadow_fb == FALSE) { 2361 /* Init fb layer */ 2362 if (!fbScreenInit(pScreen, front_ptr, 2363 pScrn->virtualX, pScrn->virtualY, 2364 pScrn->xDpi, pScrn->yDpi, pScrn->displayWidth, 2365 pScrn->bitsPerPixel)) 2366 return FALSE; 2367 } 2368 2369 xf86SetBlackWhitePixels(pScreen); 2370 2371 if (pScrn->bitsPerPixel > 8) { 2372 VisualPtr visual; 2373 2374 visual = pScreen->visuals + pScreen->numVisuals; 2375 while (--visual >= pScreen->visuals) { 2376 if ((visual->class | DynamicClass) == DirectColor) { 2377 visual->offsetRed = pScrn->offset.red; 2378 visual->offsetGreen = pScrn->offset.green; 2379 visual->offsetBlue = pScrn->offset.blue; 2380 visual->redMask = pScrn->mask.red; 2381 visual->greenMask = pScrn->mask.green; 2382 visual->blueMask = pScrn->mask.blue; 2383 } 2384 } 2385 } 2386 2387 /* Must be after RGB order fixed */ 2388 fbPictureInit (pScreen, 0, 0); 2389 2390#ifdef RENDER 2391 if ((s = xf86GetOptValString(info->Options, OPTION_SUBPIXEL_ORDER))) { 2392 if (strcmp(s, "RGB") == 0) subPixelOrder = SubPixelHorizontalRGB; 2393 else if (strcmp(s, "BGR") == 0) subPixelOrder = SubPixelHorizontalBGR; 2394 else if (strcmp(s, "NONE") == 0) subPixelOrder = SubPixelNone; 2395 PictureSetSubpixelOrder (pScreen, subPixelOrder); 2396 } 2397#endif 2398 2399 if (!pScreen->isGPU) { 2400 if (xorgGetVersion() >= XORG_VERSION_NUMERIC(1,18,3,0,0)) 2401 value = info->use_glamor; 2402 else 2403 value = FALSE; 2404 from = X_DEFAULT; 2405 2406 if (!info->r600_shadow_fb) { 2407 if (xf86GetOptValBool(info->Options, OPTION_DRI3, &value)) 2408 from = X_CONFIG; 2409 2410 if (xf86GetOptValInteger(info->Options, OPTION_DRI, &driLevel) && 2411 (driLevel == 2 || driLevel == 3)) { 2412 from = X_CONFIG; 2413 value = driLevel == 3; 2414 } 2415 } 2416 2417 if (value) { 2418 value = radeon_sync_init(pScreen) && 2419 radeon_present_screen_init(pScreen) && 2420 radeon_dri3_screen_init(pScreen); 2421 2422 if (!value) 2423 from = X_WARNING; 2424 } 2425 2426 xf86DrvMsg(pScrn->scrnIndex, from, "DRI3 %sabled\n", value ? "en" : "dis"); 2427 } 2428 2429 pScrn->vtSema = TRUE; 2430 xf86SetBackingStore(pScreen); 2431 2432 if (info->directRenderingEnabled) { 2433 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Direct rendering enabled\n"); 2434 } else { 2435 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2436 "Direct rendering disabled\n"); 2437 } 2438 2439 if (info->r600_shadow_fb) { 2440 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2441 info->accelOn = FALSE; 2442 } else { 2443 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2444 "Initializing Acceleration\n"); 2445 if (RADEONAccelInit(pScreen)) { 2446 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration enabled\n"); 2447 info->accelOn = TRUE; 2448 } else { 2449 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2450 "Acceleration initialization failed\n"); 2451 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Acceleration disabled\n"); 2452 info->accelOn = FALSE; 2453 } 2454 } 2455 2456 /* Init DPMS */ 2457 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2458 "Initializing DPMS\n"); 2459 xf86DPMSInit(pScreen, xf86DPMSSet, 0); 2460 2461 if (!RADEONCursorInit_KMS(pScreen)) 2462 return FALSE; 2463 2464 /* DGA setup */ 2465#ifdef XFreeXDGA 2466 /* DGA is dangerous on kms as the base and framebuffer location may change: 2467 * http://lists.freedesktop.org/archives/xorg-devel/2009-September/002113.html 2468 */ 2469 /* xf86DiDGAInit(pScreen, info->LinearAddr + pScrn->fbOffset); */ 2470#endif 2471 if (info->r600_shadow_fb == FALSE && !pScreen->isGPU) { 2472 /* Init Xv */ 2473 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2474 "Initializing Xv\n"); 2475 RADEONInitVideo(pScreen); 2476 } 2477 2478 if (info->r600_shadow_fb == TRUE) { 2479 if (!shadowSetup(pScreen)) { 2480 xf86DrvMsg(pScrn->scrnIndex, X_ERROR, 2481 "Shadowfb initialization failed\n"); 2482 return FALSE; 2483 } 2484 } 2485 pScrn->pScreen = pScreen; 2486 2487 if (!pScreen->isGPU) { 2488 if (serverGeneration == 1 && bgNoneRoot && info->accelOn) { 2489 info->CreateWindow = pScreen->CreateWindow; 2490 pScreen->CreateWindow = RADEONCreateWindow_oneshot; 2491 } 2492 info->WindowExposures = pScreen->WindowExposures; 2493 pScreen->WindowExposures = RADEONWindowExposures_oneshot; 2494 } 2495 2496 /* Provide SaveScreen & wrap BlockHandler and CloseScreen */ 2497 /* Wrap CloseScreen */ 2498 info->CloseScreen = pScreen->CloseScreen; 2499 pScreen->CloseScreen = RADEONCloseScreen_KMS; 2500 pScreen->SaveScreen = RADEONSaveScreen_KMS; 2501 info->BlockHandler = pScreen->BlockHandler; 2502 pScreen->BlockHandler = RADEONBlockHandler_KMS; 2503 2504 info->CreateScreenResources = pScreen->CreateScreenResources; 2505 pScreen->CreateScreenResources = RADEONCreateScreenResources_KMS; 2506 2507 pScreen->StartPixmapTracking = PixmapStartDirtyTracking; 2508 pScreen->StopPixmapTracking = PixmapStopDirtyTracking; 2509#if HAS_SYNC_SHARED_PIXMAP 2510 pScreen->SyncSharedPixmap = radeon_sync_shared_pixmap; 2511#endif 2512 2513 if (!xf86CrtcScreenInit (pScreen)) 2514 return FALSE; 2515 2516 /* Wrap pointer motion to flip touch screen around */ 2517// info->PointerMoved = pScrn->PointerMoved; 2518// pScrn->PointerMoved = RADEONPointerMoved; 2519 2520 if (!drmmode_setup_colormap(pScreen, pScrn)) 2521 return FALSE; 2522 2523 /* Note unused options */ 2524 if (serverGeneration == 1) 2525 xf86ShowUnusedOptions(pScrn->scrnIndex, pScrn->options); 2526 2527 drmmode_init(pScrn, &info->drmmode); 2528 2529 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2530 "RADEONScreenInit finished\n"); 2531 2532 info->accel_state->XInited3D = FALSE; 2533 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2534 2535 return TRUE; 2536} 2537 2538Bool RADEONEnterVT_KMS(ScrnInfoPtr pScrn) 2539{ 2540 RADEONInfoPtr info = RADEONPTR(pScrn); 2541 2542 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2543 "RADEONEnterVT_KMS\n"); 2544 2545 radeon_set_drm_master(pScrn); 2546 2547 if (info->r600_shadow_fb) { 2548 int base_align = drmmode_get_base_align(pScrn, info->pixel_bytes, 0); 2549 struct radeon_bo *front_bo = radeon_bo_open(info->bufmgr, 0, 2550 pScrn->displayWidth * 2551 info->pixel_bytes * 2552 pScrn->virtualY, 2553 base_align, 2554 RADEON_GEM_DOMAIN_VRAM, 0); 2555 2556 if (front_bo) { 2557 if (radeon_bo_map(front_bo, 1) == 0) { 2558 memset(front_bo->ptr, 0, front_bo->size); 2559 radeon_bo_unref(info->front_buffer->bo.radeon); 2560 info->front_buffer->bo.radeon = front_bo; 2561 } else { 2562 radeon_bo_unref(front_bo); 2563 front_bo = NULL; 2564 } 2565 } 2566 2567 if (!front_bo) { 2568 xf86DrvMsg(pScrn->scrnIndex, X_WARNING, 2569 "Failed to allocate new scanout BO after VT switch, " 2570 "other DRM masters may see screen contents\n"); 2571 } 2572 } 2573 2574 info->accel_state->XInited3D = FALSE; 2575 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2576 2577 pScrn->vtSema = TRUE; 2578 2579 if (!drmmode_set_desired_modes(pScrn, &info->drmmode, TRUE)) 2580 return FALSE; 2581 2582 return TRUE; 2583} 2584 2585static 2586CARD32 cleanup_black_fb(OsTimerPtr timer, CARD32 now, pointer data) 2587{ 2588 ScreenPtr screen = data; 2589 ScrnInfoPtr scrn = xf86ScreenToScrn(screen); 2590 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2591 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn); 2592 int c; 2593 2594 if (xf86ScreenToScrn(radeon_primary_screen(screen))->vtSema) 2595 return 0; 2596 2597 /* Unreference the all-black FB created by RADEONLeaveVT_KMS. After 2598 * this, there should be no FB left created by this driver. 2599 */ 2600 for (c = 0; c < xf86_config->num_crtc; c++) { 2601 drmmode_crtc_private_ptr drmmode_crtc = 2602 xf86_config->crtc[c]->driver_private; 2603 2604 drmmode_fb_reference(pRADEONEnt->fd, &drmmode_crtc->fb, NULL); 2605 } 2606 2607 TimerFree(timer); 2608 return 0; 2609} 2610 2611static void 2612pixmap_unref_fb(PixmapPtr pixmap) 2613{ 2614 ScrnInfoPtr scrn = xf86ScreenToScrn(pixmap->drawable.pScreen); 2615 struct drmmode_fb **fb_ptr = radeon_pixmap_get_fb_ptr(pixmap); 2616 RADEONEntPtr pRADEONEnt = RADEONEntPriv(scrn); 2617 2618 if (fb_ptr) 2619 drmmode_fb_reference(pRADEONEnt->fd, fb_ptr, NULL); 2620} 2621 2622static void 2623client_pixmap_unref_fb(void *value, XID id, void *pScreen) 2624{ 2625 PixmapPtr pixmap = value; 2626 2627 if (pixmap->drawable.pScreen == pScreen) 2628 pixmap_unref_fb(pixmap); 2629} 2630 2631void RADEONLeaveVT_KMS(ScrnInfoPtr pScrn) 2632{ 2633 RADEONInfoPtr info = RADEONPTR(pScrn); 2634 ScreenPtr pScreen = pScrn->pScreen; 2635 2636 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2637 "RADEONLeaveVT_KMS\n"); 2638 2639 if (!info->r600_shadow_fb) { 2640 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2641 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2642 struct drmmode_scanout black_scanout = { .pixmap = NULL, .bo = NULL }; 2643 xf86CrtcPtr crtc; 2644 drmmode_crtc_private_ptr drmmode_crtc; 2645 unsigned w = 0, h = 0; 2646 int i; 2647 2648 /* If we're called from CloseScreen, trying to clear the black 2649 * scanout BO will likely crash and burn 2650 */ 2651 if (!pScreen->GCperDepth[0]) 2652 goto hide_cursors; 2653 2654 /* Compute maximum scanout dimensions of active CRTCs */ 2655 for (i = 0; i < xf86_config->num_crtc; i++) { 2656 crtc = xf86_config->crtc[i]; 2657 drmmode_crtc = crtc->driver_private; 2658 2659 if (!drmmode_crtc->fb) 2660 continue; 2661 2662 w = max(w, crtc->mode.HDisplay); 2663 h = max(h, crtc->mode.VDisplay); 2664 } 2665 2666 /* Make all active CRTCs scan out from an all-black framebuffer */ 2667 if (w > 0 && h > 0) { 2668 if (drmmode_crtc_scanout_create(crtc, &black_scanout, w, h)) { 2669 struct drmmode_fb *black_fb = 2670 radeon_pixmap_get_fb(black_scanout.pixmap); 2671 2672 radeon_pixmap_clear(black_scanout.pixmap); 2673 radeon_finish(pScrn, black_scanout.bo); 2674 2675 for (i = 0; i < xf86_config->num_crtc; i++) { 2676 crtc = xf86_config->crtc[i]; 2677 drmmode_crtc = crtc->driver_private; 2678 2679 if (drmmode_crtc->fb) { 2680 if (black_fb) { 2681 drmmode_set_mode(crtc, black_fb, &crtc->mode, 0, 0); 2682 } else { 2683 drmModeSetCrtc(pRADEONEnt->fd, 2684 drmmode_crtc->mode_crtc->crtc_id, 0, 2685 0, 0, NULL, 0, NULL); 2686 drmmode_fb_reference(pRADEONEnt->fd, 2687 &drmmode_crtc->fb, NULL); 2688 } 2689 2690 if (pScrn->is_gpu) { 2691 if (drmmode_crtc->scanout[0].pixmap) 2692 pixmap_unref_fb(drmmode_crtc->scanout[0].pixmap); 2693 if (drmmode_crtc->scanout[1].pixmap) 2694 pixmap_unref_fb(drmmode_crtc->scanout[1].pixmap); 2695 } else { 2696 drmmode_crtc_scanout_free(crtc); 2697 } 2698 } 2699 } 2700 } 2701 } 2702 2703 xf86RotateFreeShadow(pScrn); 2704 drmmode_crtc_scanout_destroy(&info->drmmode, &black_scanout); 2705 2706 /* Unreference FBs of all pixmaps. After this, the only FB remaining 2707 * should be the all-black one being scanned out by active CRTCs 2708 */ 2709 for (i = 0; i < currentMaxClients; i++) { 2710 if (i > 0 && 2711 (!clients[i] || clients[i]->clientState != ClientStateRunning)) 2712 continue; 2713 2714 FindClientResourcesByType(clients[i], RT_PIXMAP, 2715 client_pixmap_unref_fb, pScreen); 2716 } 2717 2718 pixmap_unref_fb(pScreen->GetScreenPixmap(pScreen)); 2719 } else { 2720 memset(info->front_buffer->bo.radeon->ptr, 0, 2721 pScrn->displayWidth * info->pixel_bytes * pScrn->virtualY); 2722 } 2723 2724 if (pScreen->GCperDepth[0]) 2725 TimerSet(NULL, 0, 1000, cleanup_black_fb, pScreen); 2726 2727 hide_cursors: 2728 xf86_hide_cursors (pScrn); 2729 2730 radeon_drop_drm_master(pScrn); 2731 2732 info->accel_state->XInited3D = FALSE; 2733 info->accel_state->engineMode = EXA_ENGINEMODE_UNKNOWN; 2734 2735 xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG, 2736 "Ok, leaving now...\n"); 2737} 2738 2739 2740Bool RADEONSwitchMode_KMS(ScrnInfoPtr pScrn, DisplayModePtr mode) 2741{ 2742 Bool ret; 2743 ret = xf86SetSingleMode (pScrn, mode, RR_Rotate_0); 2744 return ret; 2745 2746} 2747 2748void RADEONAdjustFrame_KMS(ScrnInfoPtr pScrn, int x, int y) 2749{ 2750 RADEONInfoPtr info = RADEONPTR(pScrn); 2751 drmmode_adjust_frame(pScrn, &info->drmmode, x, y); 2752 return; 2753} 2754 2755static Bool radeon_setup_kernel_mem(ScreenPtr pScreen) 2756{ 2757 ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen); 2758 RADEONInfoPtr info = RADEONPTR(pScrn); 2759 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2760 int cpp = info->pixel_bytes; 2761 int pitch; 2762 uint32_t tiling_flags = 0; 2763 2764 if (info->accel_state->exa) { 2765 xf86DrvMsg(pScreen->myNum, X_ERROR, "Memory map already initialized\n"); 2766 return FALSE; 2767 } 2768 if (!info->use_glamor && info->r600_shadow_fb == FALSE) { 2769 info->accel_state->exa = exaDriverAlloc(); 2770 if (!info->accel_state->exa) { 2771 xf86DrvMsg(pScreen->myNum, X_ERROR, "exaDriverAlloc failed\n"); 2772 return FALSE; 2773 } 2774 } 2775 2776 { 2777 int cursor_size; 2778 int c, i; 2779 2780 cursor_size = info->cursor_w * info->cursor_h * 4; 2781 cursor_size = RADEON_ALIGN(cursor_size, RADEON_GPU_PAGE_SIZE); 2782 for (c = 0; c < xf86_config->num_crtc; c++) { 2783 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private; 2784 2785 for (i = 0; i < 2; i++) { 2786 if (!drmmode_crtc->cursor_bo[i]) { 2787 drmmode_crtc->cursor_bo[i] = 2788 radeon_bo_open(info->bufmgr, 0, cursor_size, 0, 2789 RADEON_GEM_DOMAIN_VRAM, 0); 2790 2791 if (!(drmmode_crtc->cursor_bo[i])) { 2792 ErrorF("Failed to allocate cursor buffer memory\n"); 2793 return FALSE; 2794 } 2795 2796 if (radeon_bo_map(drmmode_crtc->cursor_bo[i], 1)) 2797 ErrorF("Failed to map cursor buffer memory\n"); 2798 } 2799 } 2800 } 2801 } 2802 2803 if (!info->front_buffer) { 2804 int usage = CREATE_PIXMAP_USAGE_BACKING_PIXMAP; 2805 2806 if (info->allowColorTiling && !info->shadow_primary) { 2807 if (info->ChipFamily < CHIP_FAMILY_R600 || info->allowColorTiling2D) 2808 usage |= RADEON_CREATE_PIXMAP_TILING_MACRO; 2809 else 2810 usage |= RADEON_CREATE_PIXMAP_TILING_MICRO; 2811 } 2812 2813 info->front_buffer = radeon_alloc_pixmap_bo(pScrn, pScrn->virtualX, 2814 pScrn->virtualY, 2815 pScrn->depth, 2816 usage, 2817 pScrn->bitsPerPixel, 2818 &pitch, 2819 &info->front_surface, 2820 &tiling_flags); 2821 2822 if (info->r600_shadow_fb == TRUE) { 2823 if (radeon_bo_map(info->front_buffer->bo.radeon, 1)) { 2824 ErrorF("Failed to map cursor buffer memory\n"); 2825 } 2826 } 2827 2828 if (!info->use_glamor) { 2829#if X_BYTE_ORDER == X_BIG_ENDIAN 2830 switch (cpp) { 2831 case 4: 2832 tiling_flags |= RADEON_TILING_SWAP_32BIT; 2833 break; 2834 case 2: 2835 tiling_flags |= RADEON_TILING_SWAP_16BIT; 2836 break; 2837 } 2838 if (info->ChipFamily < CHIP_FAMILY_R600 && 2839 info->r600_shadow_fb && tiling_flags) 2840 tiling_flags |= RADEON_TILING_SURFACE; 2841#endif 2842 if (tiling_flags) 2843 radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, pitch); 2844 } 2845 2846 pScrn->displayWidth = pitch / cpp; 2847 } 2848 2849 pitch = pScrn->displayWidth * cpp; 2850 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Front buffer size: %dK\n", 2851 pitch * pScrn->virtualY / 1024); 2852 radeon_kms_update_vram_limit(pScrn, pitch * pScrn->virtualY); 2853 return TRUE; 2854} 2855 2856void radeon_kms_update_vram_limit(ScrnInfoPtr pScrn, uint32_t new_fb_size) 2857{ 2858 xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn); 2859 RADEONInfoPtr info = RADEONPTR(pScrn); 2860 uint64_t remain_size_bytes; 2861 int c; 2862 2863 for (c = 0; c < xf86_config->num_crtc; c++) { 2864 drmmode_crtc_private_ptr drmmode_crtc = xf86_config->crtc[c]->driver_private; 2865 2866 if (drmmode_crtc->cursor_bo[0]) 2867 new_fb_size += (64 * 4 * 64); 2868 } 2869 2870 remain_size_bytes = info->vram_size - new_fb_size; 2871 remain_size_bytes = (remain_size_bytes / 10) * 9; 2872 if (remain_size_bytes > 0xffffffff) 2873 remain_size_bytes = 0xffffffff; 2874 radeon_cs_set_limit(info->cs, RADEON_GEM_DOMAIN_VRAM, 2875 (uint32_t)remain_size_bytes); 2876 2877 xf86DrvMsg(pScrn->scrnIndex, X_INFO, "VRAM usage limit set to %uK\n", 2878 (uint32_t)remain_size_bytes / 1024); 2879} 2880 2881/* Used to disallow modes that are not supported by the hardware */ 2882ModeStatus RADEONValidMode(ScrnInfoPtr pScrn, DisplayModePtr mode, 2883 Bool verbose, int flag) 2884{ 2885 RADEONInfoPtr info = RADEONPTR(pScrn); 2886 RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn); 2887 2888 /* 2889 * RN50 has effective maximum mode bandwidth of about 300MiB/s. 2890 * XXX should really do this for all chips by properly computing 2891 * memory bandwidth and an overhead factor. 2892 */ 2893 if (info->ChipFamily == CHIP_FAMILY_RV100 && !pRADEONEnt->HasCRTC2) { 2894 if (xf86ModeBandwidth(mode, pScrn->bitsPerPixel) > 300) 2895 return MODE_BANDWIDTH; 2896 } 2897 /* There are problems with double scan mode at high clocks 2898 * They're likely related PLL and display buffer settings. 2899 * Disable these modes for now. 2900 */ 2901 if (mode->Flags & V_DBLSCAN) { 2902 if ((mode->CrtcHDisplay >= 1024) || (mode->CrtcVDisplay >= 768)) 2903 return MODE_CLOCK_RANGE; 2904 } 2905 return MODE_OK; 2906} 2907