Searched refs:outinfo (Results 1 - 12 of 12) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_shader_info.c496 return &info->vs.outinfo;
499 return &info->vs.outinfo;
503 return &info->tes.outinfo;
646 info->vs.outinfo.writes_layer = true;
649 info->tes.outinfo.writes_layer = true;
652 info->vs.outinfo.writes_layer = true;
659 struct radv_vs_output_info *outinfo = get_vs_output_info(nir, info); local in function:radv_nir_shader_info_pass
660 if (outinfo) {
662 outinfo->writes_primitive_shading_rate || device->force_vrs != RADV_FORCE_VRS_NONE;
665 if (outinfo
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H A Dradv_nir_to_llvm.c1186 unsigned noutput, struct radv_vs_output_info *outinfo,
1202 radv_export_param(ctx, outinfo->vs_output_param_offset[slot_name], outputs[i].values,
1212 unsigned noutput, struct radv_vs_output_info *outinfo, bool export_clip_dists)
1262 bool writes_primitive_shading_rate = outinfo->writes_primitive_shading_rate ||
1265 if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo->writes_layer ||
1266 outinfo->writes_viewport_index || writes_primitive_shading_rate) {
1267 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1269 (outinfo
1185 radv_build_param_exports(struct radv_shader_context * ctx,struct radv_shader_output_values * outputs,unsigned noutput,struct radv_vs_output_info * outinfo,bool export_clip_dists) argument
1211 radv_llvm_export_vs(struct radv_shader_context * ctx,struct radv_shader_output_values * outputs,unsigned noutput,struct radv_vs_output_info * outinfo,bool export_clip_dists) argument
1353 handle_vs_outputs_post(struct radv_shader_context * ctx,bool export_prim_id,bool export_clip_dists,struct radv_vs_output_info * outinfo) argument
1660 struct radv_vs_output_info *outinfo = ctx->stage == MESA_SHADER_TESS_EVAL local in function:handle_ngg_outputs_post_2
1938 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo; local in function:gfx10_ngg_gs_emit_epilogue_2
2225 struct radv_vs_output_info *outinfo; local in function:ac_nir_eliminate_const_vs_outputs
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H A Dradv_pipeline.c2074 if (!nir[MESA_SHADER_TESS_CTRL] && infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
2279 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2281 return &pipeline->gs_copy_shader->info.vs.outinfo;
2283 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2285 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2771 if (es_stage == MESA_SHADER_VERTEX && infos[es_stage].vs.outinfo.export_prim_id)
2783 infos[es_stage].vs.outinfo.export_prim_id);
2871 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id = true;
2873 infos[MESA_SHADER_TESS_EVAL].tes.outinfo.export_prim_id = true;
2881 infos[MESA_SHADER_VERTEX].vs.outinfo
4373 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_vgt_gs_mode
4410 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_hw_vs
4523 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_hw_ngg
4933 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_ps_inputs
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H A Dradv_shader.h255 struct radv_vs_output_info outinfo; member in struct:radv_shader_info::__anonc0b8b2d60608
284 struct radv_vs_output_info outinfo; member in struct:radv_shader_info::__anonc0b8b2d60808
H A Dradv_shader.c969 if (info->tes.outinfo.export_prim_id)
999 export_prim_id = info->vs.outinfo.export_prim_id;
1001 export_prim_id = info->tes.outinfo.export_prim_id;
1390 bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
1441 } else if (info->vs.outinfo.export_prim_id) {
1495 bool enable_prim_id = info->tes.outinfo.export_prim_id || info->uses_prim_id;
1506 info->vs.outinfo.export_prim_id)) {
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_instruction_selection_setup.cpp251 const radv_vs_output_info* outinfo)
253 ctx->export_clip_dists = outinfo->export_clip_dists;
254 ctx->num_clip_distances = util_bitcount(outinfo->clip_dist_mask);
255 ctx->num_cull_distances = util_bitcount(outinfo->cull_dist_mask);
265 ctx->program->early_rast = ctx->program->chip_class >= GFX10 && outinfo->param_exports == 0;
272 setup_vs_output_info(ctx, nir, &ctx->program->info->vs.outinfo);
294 setup_vs_output_info(ctx, nir, &ctx->program->info->vs.outinfo);
316 setup_vs_output_info(ctx, nir, &ctx->program->info->tes.outinfo);
900 setup_vs_output_info(&ctx, shaders[0], &args->shader_info->vs.outinfo);
250 setup_vs_output_info(isel_context * ctx,nir_shader * nir,const radv_vs_output_info * outinfo) argument
H A Daco_instruction_selection.cpp10643 ? ctx->program->info->tes.outinfo.vs_output_param_offset[slot]
10644 : ctx->program->info->vs.outinfo.vs_output_param_offset[slot];
10745 const radv_vs_output_info* outinfo = (ctx->stage.has(SWStage::TES) && !ctx->stage.has(SWStage::GS)) local in function:aco::__anon562fcc110110::create_vs_exports
10746 ? &ctx->program->info->tes.outinfo
10747 : &ctx->program->info->vs.outinfo;
10751 if (outinfo->export_prim_id && ctx->stage.hw != HWStage::NGG) {
10777 outinfo->writes_primitive_shading_rate || ctx->options->force_vrs_rates;
10778 if (outinfo->writes_pointsize || outinfo->writes_layer || outinfo
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/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_shader.h265 struct radv_vs_output_info outinfo; member in struct:radv_shader_variant_info::__anon685e57830908::__anon685e57830a08
297 struct radv_vs_output_info outinfo; member in struct:radv_shader_variant_info::__anon685e57830908::__anon685e57830f08
H A Dradv_nir_to_llvm.c2535 ctx->shader_info->vs.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2536 ctx->shader_info->vs.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2537 ctx->shader_info->vs.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2540 ctx->shader_info->tes.outinfo.clip_dist_mask = (1 << shader->info.clip_distance_array_size) - 1;
2541 ctx->shader_info->tes.outinfo.cull_dist_mask = (1 << shader->info.cull_distance_array_size) - 1;
2542 ctx->shader_info->tes.outinfo.cull_dist_mask <<= shader->info.clip_distance_array_size;
2864 struct radv_vs_output_info *outinfo)
2885 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2886 sizeof(outinfo->vs_output_param_offset));
2922 outinfo
2862 handle_vs_outputs_post(struct radv_shader_context * ctx,bool export_prim_id,bool export_layer_id,struct radv_vs_output_info * outinfo) argument
3075 handle_es_outputs_post(struct radv_shader_context * ctx,struct radv_es_output_info * outinfo) argument
3486 struct radv_vs_output_info *outinfo; local in function:ac_nir_eliminate_const_vs_outputs
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H A Dradv_pipeline.c1749 return &pipeline->gs_copy_shader->info.vs.outinfo;
1751 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1753 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2934 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_vgt_gs_mode
2948 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
2971 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_hw_vs
2973 clip_dist_mask = outinfo->clip_dist_mask;
2974 cull_dist_mask = outinfo->cull_dist_mask;
2976 bool misc_vec_ena = outinfo->writes_pointsize ||
2977 outinfo
3237 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline); local in function:radv_pipeline_generate_ps_inputs
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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.0.rst3900 - radv: remove unnecessary init of outinfo.export_prim_id for GS
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json18427 "description": "aco: Use the correct outinfo for mesh shaders.",
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