| /xsrc/external/mit/libdrm/dist/radeon/ |
| radeon_cs.h | 54 uint32_t *packets; member in struct:radeon_cs
117 cs->packets[cs->cdw++] = dword;
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t));
135 memcpy(cs->packets + cs->cdw, data, size * 4);
|
| radeon_cs_int.h | 14 uint32_t *packets; member in struct:radeon_cs_int
|
| radeon_cs_gem.c | 140 csg->base.packets = (uint32_t*)calloc(1, 64 * 1024);
141 if (csg->base.packets == NULL) {
152 free(csg->base.packets);
159 free(csg->base.packets);
165 csg->chunks[0].chunk_data = (uint64_t)(uintptr_t)csg->base.packets;
301 ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
305 cs->packets = ptr;
366 blob = bof_blob(cs->cdw * 4, cs->packets);
468 free(cs->packets);
510 fprintf(file, "0x%08X\n", cs->packets[i])
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/ |
| egd_tables.py | 147 def parse(filename, regs, packets):
191 packets.append(line.split()[0])
214 def write_tables(regs, packets):
247 for pkt in packets:
300 packets = []
302 parse(arg, regs, packets)
303 write_tables(regs, packets)
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/ |
| egd_tables.py | 149 def parse(filename, regs, packets):
193 packets.append(line.split()[0])
216 def write_tables(regs, packets):
249 for pkt in packets:
302 packets = []
304 parse(arg, regs, packets)
305 write_tables(regs, packets)
|
| /xsrc/external/mit/MesaLib/dist/src/amd/common/ |
| sid_tables.py | 233 packets = []
241 packets.append(line.split()[0])
242 return packets
251 def write(self, regdb, packets, file=sys.stdout):
283 for pkt in packets:
347 packets = parse_packet3(filp)
368 w.write(regdb, packets)
|
| /xsrc/external/mit/MesaLib.old/dist/src/amd/common/ |
| sid_tables.py | 248 def parse(self, filp, packets, older_asics):
250 Parse registers from the given header file. Packets are separately
251 stored in the packets array.
291 packets.append(line.split()[0])
332 def write_tables(asics, packets):
365 for pkt in packets:
406 packets = []
412 asic.parse(filp, packets, asics)
414 write_tables(asics, packets)
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/ |
| fd6_const.c | 266 unsigned packets, size; local
269 ir3_user_consts_size(ubo_state, &packets, &size);
272 packets += 1;
275 unsigned sizedwords = (4 * packets) + size;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/ir3/ |
| ir3_const.h | 33 * CP_LOAD_STATE packets (which is handled inside the generation
88 * Returns number of packets, and total size of all the payload.
96 ir3_user_consts_size(struct ir3_ubo_analysis_state *state, unsigned *packets,
99 *packets = *size = 0;
104 (*packets)++;
|
| /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/ |
| radeon_ioctl.c | 171 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
260 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
|
| /xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/ |
| radeon_ioctl.c | 172 uint32_t *cmd = (uint32_t *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_start);
261 retval = (GLushort *)(rmesa->radeon.cmdbuf.cs->packets + rmesa->tcl.elt_cmd_offset);
|
| /xsrc/external/mit/xf86-video-ati/dist/src/ |
| radeon_exa_render.c | 2381 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2413 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2436 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
|
| /xsrc/external/mit/xf86-video-ati-kms/dist/src/ |
| radeon_exa_render.c | 2265 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2292 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
2310 info->accel_state->draw_header = info->cs->packets + info->cs->cdw;
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/ |
| iris_state.c | 115 * Statically assert that PIPE_* enums match the hardware packets.
1147 /* Depth/HiZ/Stencil related hardware packets. */
1148 uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) + member in struct:iris_depth_buffer_state
1166 * packets which vary by generation.
3171 isl_emit_depth_stencil_hiz_s(isl_dev, cso_z->packets, &info);
3695 * 3DSTATE_SO_BUFFER packets we started earlier.
3783 * 3DSTATE_SO_BUFFER packets to reset the offset to the beginning.
3784 * Any further times we emit those packets, we want to use 0xFFFFFFFF
3823 * 3DSTATE_STREAMOUT packets.
4561 * Compute the size of the derived data (shader command packets)
[all...] |
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/ |
| iris_state.c | 180 * Statically assert that PIPE_* enums match the hardware packets.
825 /* Depth/HiZ/Stencil related hardware packets. */
826 uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) + member in struct:iris_depth_buffer_state
836 * packets which vary by generation.
2520 isl_emit_depth_stencil_hiz_s(isl_dev, cso_z->packets, &info);
3029 * 3DSTATE_SO_BUFFER packets we started earlier.
3129 * 3DSTATE_STREAMOUT packets.
3819 * Compute the size of the derived data (shader command packets).
3864 * Create any state packets corresponding to the given shader stage
4276 * We can skip buffers if we've re-emitted those packets, as we'r
[all...] |
