Searched refs:queue_idx (Results 1 - 8 of 8) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c818 int queue_idx,
878 request.ring = queue_idx;
882 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
908 int queue_idx,
964 request.ring = queue_idx;
968 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
995 int queue_idx,
1157 request.ring = queue_idx;
1161 request.fence_info = radv_set_cs_fence(ctx, cs0->hw_ip, queue_idx);
1196 int queue_idx,
817 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
907 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
994 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * radv_bo_list,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radeon_winsys_fence * _fence) argument
1195 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx * _ctx,int queue_idx,struct radeon_cmdbuf ** cs_array,unsigned cs_count,struct radeon_cmdbuf * initial_preamble_cs,struct radeon_cmdbuf * continue_preamble_cs,struct radv_winsys_sem_info * sem_info,const struct radv_winsys_bo_list * bo_list,bool can_patch,struct radeon_winsys_fence * _fence) argument
[all...]
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
H A Dradv_amdgpu_cs.c804 radv_amdgpu_winsys_cs_submit_chained(struct radeon_winsys_ctx *_ctx, int queue_idx, argument
860 request.ring = queue_idx;
882 radv_amdgpu_winsys_cs_submit_fallback(struct radeon_winsys_ctx *_ctx, int queue_idx, argument
937 request.ring = queue_idx;
960 radv_amdgpu_winsys_cs_submit_sysmem(struct radeon_winsys_ctx *_ctx, int queue_idx, argument
1118 request.ring = queue_idx;
1149 radv_amdgpu_winsys_cs_submit(struct radeon_winsys_ctx *_ctx, int queue_idx, argument
1160 result = radv_amdgpu_winsys_cs_submit_sysmem(_ctx, queue_idx, sem_info, cs_array, cs_count,
1163 result = radv_amdgpu_winsys_cs_submit_chained(_ctx, queue_idx, sem_info, cs_array, cs_count,
1166 result = radv_amdgpu_winsys_cs_submit_fallback(_ctx, queue_idx, sem_inf
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_debug.c654 if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
H A Dradv_device.c1613 queue->queue_idx = idx;
2894 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2970 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3018 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3062 queue->queue_idx);
3646 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
H A Dradv_private.h643 int queue_idx; member in struct:radv_queue
/xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
H A Dtu_private.h440 int queue_idx; member in struct:tu_queue
H A Dtu_device.c984 queue->queue_idx = idx;
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.0.rst2015 - radv: Drop radv_queue::flags/queue_family_index/queue_idx
2017 - turnip: Drop tu_queue::flags/queue_family_index/queue_idx

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