Searched refs:radeon_set_sh_reg_seq (Results 1 - 20 of 20) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/radeonsi/
H A Dsi_compute.c325 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
332 radeon_set_sh_reg_seq(cs,
492 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
496 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
554 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
622 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
634 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
644 radeon_set_sh_reg_seq(cs,
706 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
741 radeon_set_sh_reg_seq(c
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H A Dsi_build_pm4.h74 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
84 radeon_set_sh_reg_seq(cs, reg, 1);
H A Dsi_state_draw.c261 radeon_set_sh_reg_seq(cs,
277 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
282 radeon_set_sh_reg_seq(cs,
291 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
829 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
838 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
/xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/
H A Dradv_cs.h84 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
95 radeon_set_sh_reg_seq(cs, reg, 1);
H A Dradv_pipeline.c2965 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3024 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3040 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3049 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3063 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3067 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3072 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3189 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
3193 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3200 radeon_set_sh_reg_seq(c
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H A Dsi_cmd_buffer.c86 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
91 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
98 radeon_set_sh_reg_seq(cs,
H A Dradv_cmd_buffer.c648 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, count);
3697 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
4228 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
4245 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 +
4253 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
H A Dradv_device.c2375 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/radeonsi/
H A Dsi_build_pm4.h113 #define radeon_set_sh_reg_seq(reg, num) do { \ macro
121 radeon_set_sh_reg_seq(reg, 1); \
278 radeon_set_sh_reg_seq(sh_offset, 1); \
H A Dsi_compute.c373 radeon_set_sh_reg_seq(R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
398 radeon_set_sh_reg_seq(R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
429 radeon_set_sh_reg_seq(R_00B890_COMPUTE_USER_ACCUM_0, 5);
543 radeon_set_sh_reg_seq(R_00B848_COMPUTE_PGM_RSRC1, 2);
598 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 4);
662 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
672 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 2);
680 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 + (user_sgpr * 4), 1);
746 radeon_set_sh_reg_seq(grid_size_reg, 3);
759 radeon_set_sh_reg_seq(cs_user_data_re
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H A Dsi_state_draw.cpp724 radeon_set_sh_reg_seq(
739 radeon_set_sh_reg_seq(R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
744 radeon_set_sh_reg_seq(
753 radeon_set_sh_reg_seq(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
1487 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, sctx->num_vs_blit_sgprs);
1499 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
1507 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1549 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1632 radeon_set_sh_reg_seq(sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
1817 radeon_set_sh_reg_seq(sh_bas
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H A Dsi_descriptors.c2068 radeon_set_sh_reg_seq(sh_offset, count); \
2161 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 +
2176 radeon_set_sh_reg_seq(R_00B900_COMPUTE_USER_DATA_0 +
/xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
H A Dradv_cs.h98 radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
110 radeon_set_sh_reg_seq(cs, reg, 1);
H A Dsi_cmd_buffer.c77 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
85 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2);
93 radeon_set_sh_reg_seq(cs, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, 2);
112 radeon_set_sh_reg_seq(cs, R_00B890_COMPUTE_USER_ACCUM_0, 5);
145 radeon_set_sh_reg_seq(cs, R_00B838_COMPUTE_TBA_LO, 4);
410 radeon_set_sh_reg_seq(cs, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0, 4);
415 radeon_set_sh_reg_seq(cs, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0, 4);
420 radeon_set_sh_reg_seq(cs, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0, 4);
425 radeon_set_sh_reg_seq(cs, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0, 4);
542 radeon_set_sh_reg_seq(c
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H A Dradv_pipeline.c4404 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
4477 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
4499 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
4519 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4658 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4662 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4855 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4863 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
5069 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
5662 radeon_set_sh_reg_seq(c
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H A Dradv_cmd_buffer.c1020 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs);
2908 radeon_set_sh_reg_seq(cmd_buffer->cs, pgm_lo_reg, 2);
6032 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr,
6072 radeon_set_sh_reg_seq(cs, state->pipeline->graphics.vtx_base_sgpr, 1 + !!drawid);
6493 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + vp_sgpr_idx * 4, 4);
6972 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
6986 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
6993 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3);
7242 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);
H A Dradv_device.c3669 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_cs.h170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
180 radeon_set_sh_reg_seq(cs, reg, 1);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_cs.h170 static inline void radeon_set_sh_reg_seq(struct radeon_cmdbuf *cs, unsigned reg, unsigned num) function in typeref:typename:void
180 radeon_set_sh_reg_seq(cs, reg, 1);
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D21.3.0.rst3842 - radv: use radeon_set_sh_reg_seq() more for initial gfx/compute state

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