Searched refs:send (Results 1 - 25 of 168) sorted by relevance

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/xsrc/external/mit/xorg-server.old/dist/Xext/
H A Dxace.c93 XaceSendAccessRec send; member in union:XaceHook::__anon03841323010a
136 u.send.client = va_arg(ap, ClientPtr);
137 u.send.dev = va_arg(ap, DeviceIntPtr);
138 u.send.pWin = va_arg(ap, WindowPtr);
139 u.send.events = va_arg(ap, xEventPtr);
140 u.send.count = va_arg(ap, int);
141 u.send.status = Success; /* default allow */
142 prv = &u.send.status;
/xsrc/external/mit/xorg-server/dist/Xext/
H A Dxace.c74 XaceSendAccessRec send; member in union:XaceHook::__anon8c232e96010a
118 u.send.client = va_arg(ap, ClientPtr);
119 u.send.dev = va_arg(ap, DeviceIntPtr);
120 u.send.pWin = va_arg(ap, WindowPtr);
122 u.send.events = va_arg(ap, xEventPtr);
123 u.send.count = va_arg(ap, int);
125 u.send.status = Success; /* default allow */
126 prv = &u.send.status;
/xsrc/external/mit/MesaLib.old/dist/src/intel/compiler/
H A Dbrw_vec4_generator.cpp324 /* dst = send(offset, a0.0 | <descriptor>) */
774 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_tcs_urb_write
775 brw_set_dest(p, send, brw_null_reg());
776 brw_set_src0(p, send, urb_header);
777 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
779 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
780 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
781 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
783 brw_inst_set_eot(devinfo, send, 1);
785 brw_inst_set_urb_per_slot_offset(devinfo, send,
961 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_vec4_urb_read
998 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_tcs_release_input
1175 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_scratch_read
1251 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_scratch_write
1315 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_pull_constant_load
[all...]
H A Dbrw_fs_generator.cpp382 /* Check runtime bit to detect if we have to send AA data or not */
395 /* Don't send AA data */
513 * by a send, the instruction requires a “Switch”. This is to
514 * avoid race condition where send may dispatch before MRF is
698 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_urb_read
699 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
700 brw_set_src0(p, send, header);
701 brw_set_src1(p, send, brw_imm_ud(0u));
703 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
704 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_REA
1428 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_uniform_pull_constant_load_gen7
1511 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_varying_pull_constant_load_gen4
[all...]
H A Dbrw_eu_emit.c72 /* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"):
73 * "The send with EOT should use register space R112-R127 for <src>. This is
852 * may send us mixed D and UD types and want us to ignore that and use
1903 /* Example code doesn't set predicate_control for send
2110 * send from any register we want. By using the destination register
2387 * is, send). The hardware behavior is undefined if this instruction is
2392 * utilizing send with SecHalf. More importantly, SIMD8 sampler messages
2518 struct brw_inst *send; local in function:brw_send_indirect_message
2525 send = next_insn(p, BRW_OPCODE_SEND);
2526 brw_set_src0(p, send, retyp
2568 struct brw_inst *send; local in function:brw_send_indirect_split_message
3393 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_shader_time_add
[all...]
/xsrc/external/mit/MesaLib/dist/src/intel/compiler/
H A Dbrw_vec4_generator.cpp326 /* dst = send(offset, a0.0 | <descriptor>) */
773 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_tcs_urb_write
774 brw_set_dest(p, send, brw_null_reg());
775 brw_set_src0(p, send, urb_header);
776 brw_set_desc(p, send, brw_message_desc(devinfo, inst->mlen, 0, true));
778 brw_inst_set_sfid(devinfo, send, BRW_SFID_URB);
779 brw_inst_set_urb_opcode(devinfo, send, BRW_URB_OPCODE_WRITE_OWORD);
780 brw_inst_set_urb_global_offset(devinfo, send, inst->offset);
782 brw_inst_set_eot(devinfo, send, 1);
784 brw_inst_set_urb_per_slot_offset(devinfo, send,
960 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_vec4_urb_read
997 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_tcs_release_input
1174 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_scratch_read
1250 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_scratch_write
1312 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:generate_pull_constant_load
[all...]
H A Dbrw_fs_generator.cpp419 /* Check runtime bit to detect if we have to send AA data or not */
432 /* Don't send AA data */
587 * by a send, the instruction requires a “Switch”. This is to
588 * avoid race condition where send may dispatch before MRF is
834 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_urb_read
835 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
836 brw_set_src0(p, send, header);
838 brw_set_src1(p, send, brw_imm_ud(0u));
840 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
841 brw_inst_set_urb_opcode(p->devinfo, send, GFX8_URB_OPCODE_SIMD8_REA
1647 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_uniform_pull_constant_load_gfx7
1731 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:fs_generator::generate_varying_pull_constant_load_gfx4
[all...]
H A Dbrw_eu_emit.c73 /* From the Ivybridge PRM, Volume 4 Part 3, page 218 ("send"):
74 * "The send with EOT should use register space R112-R127 for <src>. This is
989 * may send us mixed D and UD types and want us to ignore that and use
2064 /* Example code doesn't set predicate_control for send
2282 * send from any register we want. By using the destination register
2558 * is, send). The hardware behavior is undefined if this instruction is
2563 * utilizing send with SecHalf. More importantly, SIMD8 sampler messages
2692 struct brw_inst *send; local in function:brw_send_indirect_message
2699 send = next_insn(p, BRW_OPCODE_SEND);
2700 brw_set_src0(p, send, retyp
2749 struct brw_inst *send; local in function:brw_send_indirect_split_message
3625 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND); local in function:brw_shader_time_add
[all...]
/xsrc/external/mit/MesaLib/dist/src/vulkan/overlay-layer/
H A Dmesa-overlay-control.py65 def send(self, msg): member in class:Connection
66 self.sock.send(msg)
188 conn.send(bytearray(':capture=1;', 'utf-8'))
190 conn.send(bytearray(':capture=0;', 'utf-8'))
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D10.5.8.rst48 - i965: Disable compaction for EOT send messages
75 - i965/fs: Don't let the EOT send message interfere with the MRF hack
H A D9.2.1.rst136 - i965/vs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
137 - i965/fs: Detect GRF sources in split_virtual_grfs send-from-GRF code.
H A D18.1.4.rst83 send
H A D19.0.7.rst56 - winsys/svga/drm: Fix 32-bit RPCI send message
/xsrc/external/mit/MesaLib/dist/src/util/
H A Dos_socket.c64 return send(socket, buffer, length, flags);
/xsrc/external/mit/xedit/dist/lisp/
H A Dpathname.c487 string[PATH_MAX + 1], *send; local in function:Lisp_ParseNamestring
501 send = ptr + alength;
502 while (ptr < send) {
504 for (str = ptr; str < send && *str == PATH_SEP; str++)
509 send -= str - ptr;
549 send = data + alength;
552 for (str = ptr; str < send; str++) {
556 while (str < send) {
563 for (ptr = str; str < send; str++) {
584 send
[all...]
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/util/
H A Du_network.c84 return send(s, data, size, 0);
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/util/
H A Du_network.c84 return send(s, data, size, 0);
/xsrc/external/mit/glu/dist/src/libnurbs/internals/
H A Dmapdesc.cc581 for( REAL *send=src+stride*order; src!=send; send-=stride, dst+=stride ) { local in function:Mapdesc::subdivide
584 for( REAL *qp=src; qpnt!=send; qp=qpnt, qpnt+=stride )
603 for( REAL *send = src+ts*to; sp != send; send -= ts, dp += ts ) { local in function:Mapdesc::subdivide
606 for( REAL *qpnt = sp+ts; qpnt != send; qp = qpnt, qpnt += ts )
/xsrc/external/mit/xf86-video-ati/xorg-server-copy/
H A Dmsp3430.c72 I2CByte send[3]; local in function:GetMSP3430Data
75 send[0] = RegAddress;
76 send[1] = RegSubAddressHigh;
77 send[2] = RegSubAddressLow;
79 I2C_WriteRead(&(m->d), send, 3, receive, 2);
/xsrc/external/mit/xorg-server.old/dist/hw/xfree86/i2c/
H A Dmsp3430.c72 I2CByte send[3]; local in function:GetMSP3430Data
75 send[0] = RegAddress;
76 send[1] = RegSubAddressHigh;
77 send[2] = RegSubAddressLow;
79 I2C_WriteRead(&(m->d), send, 3, receive, 2);
/xsrc/external/mit/libdrm/dist/
H A DCONTRIBUTING.rst8 send-email. For patches only touching driver specific code one of the driver
81 To apply for commit rights ("Developer" role in gitlab) send a mail to
/xsrc/external/mit/xf86-video-qxl/dist/src/
H A Dspiceqxl_vdagent.c40 written = send(virtio_client_fd, buf, len, 0);
/xsrc/external/mit/MesaLib/dist/docs/
H A Dthanks.rst65 Apologies to anyone who's been omitted. Please send corrections and
/xsrc/external/mit/MesaLib/dist/src/gallium/winsys/svga/drm/
H A Dvmw_msg.c455 msg_arg.send = (uint64_t) (unsigned long) (msg);
469 debug_printf("Failed to send log\n");
H A Dvmwgfx_drm.h1229 * @send: Pointer to user-space msg string (null terminated).
1236 __u64 send; member in struct:drm_vmw_msg_arg

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