Searched refs:shifts (Results 1 - 25 of 34) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/panfrost/lib/
H A Dpan_encoder.h163 /* The values needing packing, in order, and the corresponding shifts.
167 unsigned shifts[7] = { 0 }; local in function:panfrost_pack_work_groups_compute
175 packed |= ((values[i] - 1) << shifts[i]);
181 shifts[i + 1] = shifts[i] + bit_count;
186 cfg.size_y_shift = shifts[1];
187 cfg.size_z_shift = shifts[2];
188 cfg.workgroups_x_shift = shifts[3];
192 cfg.workgroups_y_shift = shifts[4];
193 cfg.workgroups_z_shift = shifts[
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/common/
H A Dutils.c182 int shifts[4]; member in struct:driCreateConfigs::__anon3f6f77670108
220 const int * shifts; local in function:driCreateConfigs
236 shifts = format_table[0].shifts;
241 shifts = format_table[1].shifts;
246 shifts = format_table[2].shifts;
251 shifts = format_table[5].shifts;
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/xsrc/external/mit/MesaLib/dist/src/amd/registers/
H A Dparse_kernel_headers.py695 shifts = {}
712 d = shifts if is_shift else masks
759 if name in shifts and name in masks:
760 for (field, shift) in shifts[name].items():
/xsrc/external/mit/MesaLib/dist/src/intel/common/tests/
H A Dmi_builder_test.cpp717 uint32_t shifts[] = { 0, 1, 2, 4, 8, 16, 32 }; local in function:TEST_F
718 memcpy(input + 8, shifts, sizeof(shifts));
720 for (unsigned i = 0; i < ARRAY_SIZE(shifts); i++) {
727 for (unsigned i = 0; i < ARRAY_SIZE(shifts); i++) {
729 mi_ishl(&b, mi_imm(value), mi_imm(shifts[i])));
738 uint32_t shifts[] = { 0, 1, 2, 4, 8, 16, 32 }; local in function:TEST_F
739 memcpy(input + 8, shifts, sizeof(shifts));
741 for (unsigned i = 0; i < ARRAY_SIZE(shifts);
780 uint32_t shifts[] = { 0, 1, 2, 4, 8, 16, 32 }; local in function:TEST_F
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/xsrc/external/mit/MesaLib/dist/src/egl/drivers/dri2/
H A Dplatform_drm.c100 int shifts[4]; local in function:dri2_drm_config_is_compatible
110 dri2_get_shifts_and_sizes(dri2_dpy->core, config, shifts, sizes);
123 if (shifts[0] != visual->rgba_shifts.red ||
124 shifts[1] != visual->rgba_shifts.green ||
125 shifts[2] != visual->rgba_shifts.blue ||
126 (shifts[3] > -1 && visual->rgba_shifts.alpha > -1 &&
127 shifts[3] != visual->rgba_shifts.alpha) ||
623 int shifts[4]; local in function:drm_add_configs_for_visuals
627 dri2_get_shifts_and_sizes(dri2_dpy->core, config, shifts, sizes);
634 if (visuals[j].rgba_shifts.red != shifts[
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H A Degl_dri2.c331 const __DRIconfig *config, int *shifts,
336 if (core->getConfigAttrib(config, __DRI_ATTRIB_RED_SHIFT, (unsigned int *)&shifts[0])) {
337 core->getConfigAttrib(config, __DRI_ATTRIB_GREEN_SHIFT, (unsigned int *)&shifts[1]);
338 core->getConfigAttrib(config, __DRI_ATTRIB_BLUE_SHIFT, (unsigned int *)&shifts[2]);
339 core->getConfigAttrib(config, __DRI_ATTRIB_ALPHA_SHIFT, (unsigned int *)&shifts[3]);
341 /* Driver isn't exposing shifts, so convert masks to shifts */
343 shifts[0] = ffs(mask) - 1;
345 shifts[1] = ffs(mask) - 1;
347 shifts[
330 dri2_get_shifts_and_sizes(const __DRIcoreExtension * core,const __DRIconfig * config,int * shifts,unsigned int * sizes) argument
373 int shifts[4]; local in function:dri2_image_format_for_pbuffer_config
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H A Dplatform_wayland.c163 int shifts[4]; local in function:dri2_wl_visual_idx_from_config
166 dri2_get_shifts_and_sizes(dri2_dpy->core, config, shifts, sizes);
171 int cmp_rgb_shifts = memcmp(shifts, wl_visual->rgba_shifts,
172 3 * sizeof(shifts[0]));
177 wl_visual->rgba_shifts[3] == (force_opaque ? -1 : shifts[3]) &&
H A Degl_dri2.h436 const __DRIconfig *config, int *shifts,
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_format_aos.c227 LLVMValueRef shifts[4]; local in function:lp_build_unpack_arith_rgba_aos
269 shifts[i] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
282 shifts[i] = lp_build_const_int32(gallivm, shift);
303 * several vector shifts and shuffle/blend results together.
328 shifted = LLVMBuildLShr(builder, packed, LLVMConstVector(shifts, 4), "");
373 LLVMValueRef shifts[4]; local in function:lp_build_pack_rgba_aos
406 shifts[i] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
415 shifts[i] = lp_build_const_int32(gallivm, shift);
433 shifted = LLVMBuildShl(builder, casted, LLVMConstVector(shifts, 4), "");
H A Dlp_bld_swizzle.c189 * Bit mask and shifts
246 * Bit mask and recursive shifts
264 * shifts[] gives little-endian shift amounts; we need to negate for big-endian.
267 const int shifts[4][2] = { local in function:lp_build_swizzle_scalar_aos
293 int shift = shifts[channel][i];
450 * Bit mask and shifts.
497 * same shift as possible. The shift amount is positive for shifts left
498 * and negative for shifts right.
/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/gallivm/
H A Dlp_bld_format_aos.c227 LLVMValueRef shifts[4]; local in function:lp_build_unpack_arith_rgba_aos
269 shifts[i] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
282 shifts[i] = lp_build_const_int32(gallivm, shift);
303 * several vector shifts and shuffle/blend results together.
328 shifted = LLVMBuildLShr(builder, packed, LLVMConstVector(shifts, 4), "");
373 LLVMValueRef shifts[4]; local in function:lp_build_pack_rgba_aos
406 shifts[i] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
415 shifts[i] = lp_build_const_int32(gallivm, shift);
433 shifted = LLVMBuildShl(builder, casted, LLVMConstVector(shifts, 4), "");
H A Dlp_bld_swizzle.c190 * Bit mask and shifts
247 * Bit mask and recursive shifts
265 * shifts[] gives little-endian shift amounts; we need to negate for big-endian.
268 const int shifts[4][2] = { local in function:lp_build_swizzle_scalar_aos
294 int shift = shifts[channel][i];
453 * Bit mask and shifts.
500 * same shift as possible. The shift amount is positive for shifts left
501 * and negative for shifts right.
/xsrc/external/mit/libX11/dist/src/xlibi18n/
H A DlcGeneric.c789 } shifts[] = { local in function:load_generic
803 for (j = 0; shifts[j].str; j++) {
804 if (!_XlcNCompareISOLatin1(tmp, shifts[j].str,
805 (int) strlen(shifts[j].str))) {
806 type = shifts[j].type;
807 tmp += strlen(shifts[j].str);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_128_avx2.inl32 // Only 2 shifts and 2 gathers were introduced with AVX 2
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/swr/rasterizer/common/
H A Dsimdlib_128_avx2.inl32 // Only 2 shifts and 2 gathers were introduced with AVX 2
/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D17.2.3.rst85 - nv50/ir: fix 64-bit integer shifts
H A D17.3.1.rst142 - nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
H A D17.2.7.rst195 - nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
H A D19.3.0.rst172 - gallium: Fix a bunch of undefined left-shifts in u_format\_\*
2142 - egl: Convert configs to use shifts and sizes instead of masks
2143 - glx: Add fields for color shifts
2883 - freedreno/drm: fix 64b iova shifts
2902 - freedreno/ir3: handle multi component alu src when propagating shifts
H A D19.1.0.rst1120 - nir: Define shifts according to SM5 specification.
2213 - intel/common: Support bigger right-shifts with mi_builder
4324 - ac: fix 16-bit shifts
H A D20.1.0.rst908 - pan/midgard: Lower bitfield extract to shifts
2975 shifts
3565 - nir/lower_bit_size: fix lowering of shifts
H A D20.3.0.rst621 - pan/bi: Use 8-bit shifts
3372 - glsl_to_nir: fix crashes with int16 shifts
3516 - nir/algebraic: always lower idiv to shifts if bitops are allowed
/xsrc/external/mit/MesaLib/dist/src/panfrost/util/
H A Dpan_lower_framebuffer.c268 nir_ssa_def *shifts = nir_imm_ivec4(b, 8 - x, 8 - y, 8 - z, 8 - w); local in function:pan_pack_norm
277 nir_ssa_def *s = nir_ishl(b, u8, shifts);
/xsrc/external/mit/MesaLib/dist/src/amd/compiler/
H A Daco_optimizer.cpp1157 unsigned shifts = (instr->opcode == aco_opcode::ds_write2_b64 || local in function:aco::label_instruction
1162 if ((offset & mask) == 0 && ds.offset0 + (offset >> shifts) <= 255 &&
1163 ds.offset1 + (offset >> shifts) <= 255) {
1165 ds.offset0 += offset >> shifts;
1166 ds.offset1 += offset >> shifts;
/xsrc/external/mit/MesaLib/dist/docs/isl/
H A Dtiling.rst300 to a set of bit shifts and ORs. By far the simplest formulation, however, is

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