Searched refs:sq_gpr_resource_mgmt_1 (Results 1 - 10 of 10) sorted by relevance

/xsrc/external/mit/xf86-video-ati/dist/src/
H A Devergreen_accel.c137 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; local in function:evergreen_sq_setup
160 sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) |
189 E32(sq_gpr_resource_mgmt_1);
H A Dr6xx_accel.c174 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; local in function:r600_sq_setup
194 sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) |
214 E32(ib, sq_gpr_resource_mgmt_1);
/xsrc/external/mit/xf86-video-ati-kms/dist/src/
H A Devergreen_accel.c134 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; local in function:evergreen_sq_setup
157 sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) |
186 E32(sq_gpr_resource_mgmt_1);
H A Dr6xx_accel.c129 uint32_t sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; local in function:r600_sq_setup
149 sq_gpr_resource_mgmt_1 = ((sq_conf->num_ps_gprs << NUM_PS_GPRS_shift) |
169 E32(sq_gpr_resource_mgmt_1);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/r600/
H A Dr600_state.c1659 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2017 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2018 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2080 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2081 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
H A Dr600_pipe.h228 unsigned sq_gpr_resource_mgmt_1; member in struct:r600_config_state
H A Devergreen_state.c986 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
4666 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4667 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4725 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4728 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/r600/
H A Dr600_state.c1662 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1);
2020 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2021 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
2083 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp || rctx->config_state.sq_gpr_resource_mgmt_2 != tmp2) {
2084 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp;
H A Dr600_pipe.h228 unsigned sq_gpr_resource_mgmt_1; member in struct:r600_config_state
H A Devergreen_state.c992 radeon_emit(cs, a->sq_gpr_resource_mgmt_1);
4698 cur_gprs[R600_HW_STAGE_PS] = G_008C04_NUM_PS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4699 cur_gprs[R600_HW_STAGE_VS] = G_008C04_NUM_VS_GPRS(rctx->config_state.sq_gpr_resource_mgmt_1);
4757 if (rctx->config_state.sq_gpr_resource_mgmt_1 != tmp[0] ||
4760 rctx->config_state.sq_gpr_resource_mgmt_1 = tmp[0];

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