| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/lima/ir/pp/ |
| nir.c | 176 unsigned src_mask; local
179 src_mask = 0b0011;
182 src_mask = 0b0111;
185 src_mask = 0b1111;
188 src_mask = pd->write_mask;
199 ppir_node_add_src(block->comp, &node->node, ps, &ns->src, src_mask);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/lima/ir/pp/ |
| liveness.c | 32 uint8_t *dest_mask, uint8_t *src_mask)
38 dest_mask[i] |= src_mask[i];
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| nir.c | 180 unsigned src_mask; local
183 src_mask = 0b0111;
186 src_mask = 0b1111;
189 src_mask = pd->write_mask;
200 ppir_node_add_src(block->comp, &node->node, ps, &ns->src, src_mask);
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| /xsrc/external/mit/MesaLib/dist/src/mesa/program/ |
| prog_optimize.c | 121 get_dst_mask_for_mov(const struct prog_instruction *mov, GLuint src_mask)
134 if ((src_mask & (1 << src_comp)) == 0)
487 GLuint dst_mask, src_mask; local
495 src_mask = get_src_arg_mask(mov, 0, NO_MASK);
544 src_mask = get_src_arg_mask(mov, 0, dst_mask);
551 src_mask &= ~inst2->DstReg.WriteMask;
552 dst_mask &= get_dst_mask_for_mov(mov, src_mask);
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| /xsrc/external/mit/MesaLib.old/dist/src/mesa/program/ |
| prog_optimize.c | 121 get_dst_mask_for_mov(const struct prog_instruction *mov, GLuint src_mask)
134 if ((src_mask & (1 << src_comp)) == 0)
487 GLuint dst_mask, src_mask; local
495 src_mask = get_src_arg_mask(mov, 0, NO_MASK);
544 src_mask = get_src_arg_mask(mov, 0, dst_mask);
551 src_mask &= ~inst2->DstReg.WriteMask;
552 dst_mask &= get_dst_mask_for_mov(mov, src_mask);
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| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/util/ |
| u_surface.c | 530 uint64_t src_mask; local
533 src_mask = 0x00000000ffffffffull;
535 src_mask = 0x000000ff00000000ull;
540 uint64_t tmp = *row & ~src_mask;
541 *row++ = tmp | (zstencil & src_mask);
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/util/ |
| u_surface.c | 598 uint64_t src_mask; local
601 src_mask = 0x00000000ffffffffull;
603 src_mask = 0x000000ff00000000ull;
608 uint64_t tmp = *row & ~src_mask;
609 *row++ = tmp | (zstencil & src_mask);
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| /xsrc/external/mit/xorg-server.old/dist/hw/dmx/glxProxy/ |
| glxsingle.c | 917 unsigned char src_mask = 0x80; local
923 if ( *src & src_mask ) {
936 if (src_mask > 1) src_mask >>= 1;
938 src_mask = 0x80;
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| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 1118 * dst = iround(src * dst_mask / src_mask)
1122 * dst = src * (2*dst_mask + sign(src)*src_mask) / (2*src_mask)
1126 * src_mask = (1 << src_bits) - 1
1192 * Approximate the division by src_mask with a src_bits shift.
1737 LLVMValueRef src_mask[4 * 4]; local
1924 src_mask[i*2 + 0] = lp_build_extract_range(gallivm, fs_mask[i],
1926 src_mask[i*2 + 1] = lp_build_extract_range(gallivm, fs_mask[i],
1933 src_mask[i] = fs_mask[i];
2135 lp_bld_quad_twiddle(gallivm, mask_type, &src_mask[0], block_height, &src_mask[0])
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/llvmpipe/ |
| lp_state_fs.c | 1688 * dst = iround(src * dst_mask / src_mask)
1692 * dst = src * (2*dst_mask + sign(src)*src_mask) / (2*src_mask)
1696 * src_mask = (1 << src_bits) - 1
1771 * Approximate the division by src_mask with a src_bits shift.
2321 LLVMValueRef src_mask[4 * 4]; local
2508 src_mask[i*2 + 0] = lp_build_extract_range(gallivm, fs_mask[i],
2510 src_mask[i*2 + 1] = lp_build_extract_range(gallivm, fs_mask[i],
2517 src_mask[i] = fs_mask[i];
2719 lp_bld_quad_twiddle(gallivm, mask_type, &src_mask[0], block_height, &src_mask[0])
[all...] |
| /xsrc/external/mit/MesaLib/dist/src/compiler/nir/ |
| nir_format_convert.h | 57 uint32_t src_mask, int src_left_shift)
59 return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
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| /xsrc/external/mit/MesaLib.old/dist/src/compiler/nir/ |
| nir_format_convert.h | 48 uint32_t src_mask, int src_left_shift)
50 return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
|
| nir_builder.h | 812 nir_component_mask_t src_mask = local
814 dest[i] = nir_pack_bits(b, nir_channels(b, src, src_mask),
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| /xsrc/external/mit/MesaLib/dist/src/panfrost/midgard/ |
| disassemble.c | 663 uint8_t src_mask, bool is_int,
672 print_vec_swizzle(fp, src->swizzle, src->expand_mode, mode, src_mask);
867 uint8_t src_mask = local
877 shrink_mode, src_mask, is_int, argmod);
890 shrink_mode, src_mask, is_int, argmod);
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| /xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/ |
| anv_blorp.c | 297 VkImageAspectFlags src_mask = pRegions[r].srcSubresource.aspectMask, local
300 assert(anv_image_aspects_compatible(src_mask, dst_mask));
302 if (util_bitcount(src_mask) > 1) {
304 anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
329 get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
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| /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/ |
| anv_blorp.c | 353 VkImageAspectFlags src_mask = region->srcSubresource.aspectMask, local
356 assert(anv_image_aspects_compatible(src_mask, dst_mask));
358 if (util_bitcount(src_mask) > 1) {
359 anv_foreach_image_aspect_bit(aspect_bit, src_image, src_mask) {
400 get_blorp_surf_for_anv_image(cmd_buffer->device, src_image, src_mask,
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| /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/ |
| tu_cmd_buffer.c | 2646 enum tu_cmd_access_mask src_mask,
2651 if (src_mask & TU_ACCESS_SYSMEM_WRITE) {
2655 if (src_mask & TU_ACCESS_CP_WRITE) {
2664 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2676 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
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| /xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/tgsi/ |
| tgsi_lowering.c | 114 const struct tgsi_full_src_register *src, unsigned src_mask)
122 if (src_mask & (1 << i))
|
| /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_query_hw_sm.c | 600 uint32_t src_mask; /* mask for signal selection (only for NVC0:NVE4) */ member in struct:nvc0_hw_sm_counter_cfg
2449 mask_sel &= cfg->ctr[i].src_mask;
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/tgsi/ |
| tgsi_lowering.c | 113 const struct tgsi_full_src_register *src, unsigned src_mask)
121 if (src_mask & (1 << i))
|
| /xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/nouveau/nvc0/ |
| nvc0_query_hw_sm.c | 600 uint32_t src_mask; /* mask for signal selection (only for NVC0:NVE4) */ member in struct:nvc0_hw_sm_counter_cfg
2445 mask_sel &= cfg->ctr[i].src_mask;
|
| /xsrc/external/mit/pixman/dist/pixman/ |
| pixman-vmx.c | 211 #define DECLARE_SRC_MASK_VAR vector unsigned char src_mask
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