Searched refs:state_size (Results 1 - 25 of 29) sorted by relevance

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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_tcl.c291 GLuint state_size; local in function:radeonEnsureEmitSize
316 state_size = radeonCountStateEmitSize( &rmesa->radeon );
319 state_size += rmesa->hw.tcl.check( &rmesa->radeon.glCtx, &rmesa->hw.tcl );
346 return space_required + state_size;
H A Dradeon_swtcl.c237 const int state_size = radeonCountStateEmitSize( &rmesa->radeon ); local in function:radeon_predict_emit_size
243 state_size +
248 rmesa->radeon.swtcl.emit_prediction = state_size;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_tcl.c290 GLuint state_size; local in function:radeonEnsureEmitSize
315 state_size = radeonCountStateEmitSize( &rmesa->radeon );
318 state_size += rmesa->hw.tcl.check( &rmesa->radeon.glCtx, &rmesa->hw.tcl );
345 return space_required + state_size;
H A Dradeon_swtcl.c236 const int state_size = radeonCountStateEmitSize( &rmesa->radeon ); local in function:radeon_predict_emit_size
242 state_size +
247 rmesa->radeon.swtcl.emit_prediction = state_size;
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_tcl.c296 GLuint state_size; local in function:r200EnsureEmitSize
311 state_size = radeonCountStateEmitSize( &rmesa->radeon );
314 state_size += rmesa->hw.vtx.check(&rmesa->radeon.glCtx, &rmesa->hw.vtx);
341 if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __func__))
344 return space_required + state_size;
H A Dr200_state_init.c666 int state_size = TEX_STATE_SIZE_NEWDRM; local in function:r200InitState
669 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
670 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
674 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
675 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
678 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
679 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
680 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
681 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
H A Dr200_swtcl.c208 const int state_size = radeonCountStateEmitSize(&rmesa->radeon); local in function:r200_predict_emit_size
210 state_size +
215 rmesa->radeon.swtcl.emit_prediction = state_size;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/r200/
H A Dr200_tcl.c296 GLuint state_size; local in function:r200EnsureEmitSize
311 state_size = radeonCountStateEmitSize( &rmesa->radeon );
314 state_size += rmesa->hw.vtx.check(&rmesa->radeon.glCtx, &rmesa->hw.vtx);
341 if (rcommonEnsureCmdBufSpace(&rmesa->radeon, space_required + state_size, __func__))
344 return space_required + state_size;
H A Dr200_state_init.c666 int state_size = TEX_STATE_SIZE_NEWDRM; local in function:r200InitState
669 ALLOC_STATE( tex[0], tex_pair_mm, state_size, "TEX/tex-0", 0 );
670 ALLOC_STATE( tex[1], tex_pair_mm, state_size, "TEX/tex-1", 1 );
674 ALLOC_STATE( tex[0], tex_mm, state_size, "TEX/tex-0", 0 );
675 ALLOC_STATE( tex[1], tex_mm, state_size, "TEX/tex-1", 1 );
678 ALLOC_STATE( tex[2], tex_mm, state_size, "TEX/tex-2", 2 );
679 ALLOC_STATE( tex[3], tex_mm, state_size, "TEX/tex-3", 3 );
680 ALLOC_STATE( tex[4], tex_mm, state_size, "TEX/tex-4", 4 );
681 ALLOC_STATE( tex[5], tex_mm, state_size, "TEX/tex-5", 5 );
H A Dr200_swtcl.c208 const int state_size = radeonCountStateEmitSize(&rmesa->radeon); local in function:r200_predict_emit_size
210 state_size +
215 rmesa->radeon.swtcl.emit_prediction = state_size;
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_blorp.c148 unsigned state_size,
163 state_size, state_alignment,
146 blorp_alloc_binding_table(struct blorp_batch * blorp_batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A DgenX_blorp_exec.c132 unsigned state_size, unsigned state_alignment,
145 state_size, state_alignment,
131 blorp_alloc_binding_table(struct blorp_batch * batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_blorp.c175 unsigned state_size,
187 state_size, state_alignment,
173 blorp_alloc_binding_table(struct blorp_batch * blorp_batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_blorp.c155 unsigned state_size,
170 state_size, state_alignment,
153 blorp_alloc_binding_table(struct blorp_batch * blorp_batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A DgenX_blorp_exec.c145 unsigned state_size, unsigned state_alignment,
158 state_size, state_alignment,
144 blorp_alloc_binding_table(struct blorp_batch * batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A DgenX_blorp_exec.c110 unsigned state_size, unsigned state_alignment,
109 blorp_alloc_binding_table(struct blorp_batch * batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
H A Danv_allocator.c960 uint32_t state_size,
977 if (state_size >= block_size)
978 return anv_block_pool_alloc(block_pool, state_size, padding);
981 block.u64 = __sync_fetch_and_add(&pool->block.u64, state_size);
987 new.next = offset + state_size;
958 anv_fixed_size_state_pool_alloc_new(struct anv_fixed_size_state_pool * pool,struct anv_block_pool * block_pool,uint32_t state_size,uint32_t block_size,uint32_t * padding) argument
H A Danv_image.c274 unsigned state_size = clear_color_state_size + 4; local in function:add_aux_state_tracking_buffer
280 state_size += anv_minify(image->extent.depth, l) * 4;
282 state_size += image->levels * image->array_size * 4;
289 image->planes[plane].size += state_size;
290 image->size += state_size;
/xsrc/external/mit/libXi/dist/src/
H A DXExtInt.c1267 int state_size; local in function:copyDeviceChangedEvent
1272 &state_size, &labels_size);
1276 bout->state.mask = next_block(&ptr, state_size);
1746 int state_size; local in function:copy_classes
1752 &struct_size, &state_size,
1760 cls_lib->state.mask_len = state_size;
1761 cls_lib->state.mask = next_block(&ptr_lib, state_size);
1764 if (state_size != wire_mask_size)
1766 state_size - wire_mask_size);
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A DgenX_blorp_exec.c155 unsigned state_size, unsigned state_alignment,
154 blorp_alloc_binding_table(struct blorp_batch * batch,unsigned num_entries,unsigned state_size,unsigned state_alignment,uint32_t * bt_offset,uint32_t * surface_offsets,void ** surface_maps) argument
H A Danv_allocator.c879 uint32_t state_size,
896 if (state_size >= block_size)
897 return anv_block_pool_alloc(block_pool, state_size, padding);
900 block.u64 = __sync_fetch_and_add(&pool->block.u64, state_size);
906 new.next = offset + state_size;
877 anv_fixed_size_state_pool_alloc_new(struct anv_fixed_size_state_pool * pool,struct anv_block_pool * block_pool,uint32_t state_size,uint32_t block_size,uint32_t * padding) argument
H A Danv_image.c469 unsigned state_size = clear_color_state_size + 4; local in function:add_aux_state_tracking_buffer
475 state_size += anv_minify(image->vk.extent.depth, l) * 4;
477 state_size += image->vk.mip_levels * image->vk.array_layers * 4;
491 ANV_OFFSET_IMPLICIT, state_size, 4096,
/xsrc/external/mit/MesaLib.old/dist/src/mesa/main/
H A Dffvertex_prog.c1514 struct ureg state_size = register_param2(p, STATE_INTERNAL, STATE_POINT_SIZE_CLAMPED); local in function:build_atten_pointsize
1532 emit_op2(p, OPCODE_MUL, out, WRITEMASK_X, ut, state_size);
1537 emit_op2(p, OPCODE_MUL, ut, WRITEMASK_X, ut, state_size);
1538 emit_op2(p, OPCODE_MAX, ut, WRITEMASK_X, ut, swizzle1(state_size, Y));
1539 emit_op2(p, OPCODE_MIN, out, WRITEMASK_X, ut, swizzle1(state_size, Z));
/xsrc/external/mit/MesaLib/dist/src/mesa/main/
H A Dffvertex_prog.c1589 struct ureg state_size = register_param1(p, STATE_POINT_SIZE_CLAMPED); local in function:build_atten_pointsize
1607 emit_op2(p, OPCODE_MUL, out, WRITEMASK_X, ut, state_size);
1612 emit_op2(p, OPCODE_MUL, ut, WRITEMASK_X, ut, state_size);
1613 emit_op2(p, OPCODE_MAX, ut, WRITEMASK_X, ut, swizzle1(state_size, Y));
1614 emit_op2(p, OPCODE_MIN, out, WRITEMASK_X, ut, swizzle1(state_size, Z));
/xsrc/external/mit/MesaLib/dist/src/intel/blorp/
H A Dblorp_genX_exec.h85 unsigned state_size, unsigned state_alignment,
2018 unsigned *state_size)
2028 *state_size = 0;
2065 *state_size = push_const_size;
2014 blorp_get_compute_push_const(struct blorp_batch * batch,const struct blorp_params * params,uint32_t threads,uint32_t * state_offset,unsigned * state_size) argument

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