Searched refs:subgroup (Results 1 - 25 of 26) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/virtio/vulkan/
H A Dvn_physical_device.c390 VkPhysicalDeviceSubgroupProperties subgroup; member in struct:vn_physical_device_init_properties::__anon3c1368880208
421 local_props.id.pNext = &local_props.subgroup;
422 local_props.subgroup.sType =
424 local_props.subgroup.pNext = &local_props.point_clipping;
493 vk11_props->subgroupSize = local_props.subgroup.subgroupSize;
495 local_props.subgroup.supportedStages;
497 local_props.subgroup.supportedOperations;
499 local_props.subgroup.quadOperationsInAllStages;
1817 VkPhysicalDeviceSubgroupProperties *subgroup; member in union:vn_GetPhysicalDeviceProperties2::__anon3c136888040a
1861 u.subgroup
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/xsrc/external/mit/MesaLib/dist/docs/relnotes/
H A D18.1.1.rst48 - radv: Only expose subgroup shuffles on VI+.
H A D20.0.3.rst158 - radv/gfx10: fix required subgroup size with
184 - radv/llvm: fix subgroup shuffle for chips without bpermute
H A D20.3.3.rst119 - nir/load_store_vectorize: don't ignore subgroup memory barriers
H A D18.3.5.rst49 - [BSW BXT GLK] dEQP-VK.subgroups.arithmetic.subgroup regressions
H A D21.1.0.rst1368 - aco: fix VCC hint on boolean subgroup operations
1619 - gallivm: add subgroup vote 64-bit and feq support.
1621 - gallivm: add subgroup system values support
1622 - gallivm: add subgroup elect intrinsic support.
1623 - gallivm: add subgroup reduction + in/ex scan support
1624 - gallivm: add subgroup ballot support
1625 - gallivm: add subgroup read invocation support
1626 - gallivm: add subgroup lowering support
1627 - gallivm: add compute shader subgroup system values support
2596 - intel/fs: Allow compute dispatch without a pushed subgroup I
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H A D20.0.0.rst164 func.shader-subgroup-vote.basic.q0
2277 - radeonsi/nir: implement subgroup system values for SPIR-V
3080 - radv: disable subgroup shuffle operations on GFX10
3089 - radv: fix reporting subgroup size with
3413 - aco/wave32: Allow setting the subgroup ballot size to 64-bit.
H A D21.2.0.rst1512 - tu, ir3: Plumb through support for CS subgroup size/id
1525 - ir3: Add subgroup pseudoinstructions
1527 - ir3: Implement nir subgroup intrinsics
1530 - tu: Update subgroup properties
2654 - broadcom/compiler: implement more subgroup intrinsics
2657 - broadcom/compiler: track if a compute shader uses subgroup functionality
2659 - v3dv: expose correct subgroup size
2660 - v3dv: expose support for basic subgroup operations
3483 - radeonsi: allow changing the NGG subgroup size to 256 but don't change it yet
H A D21.3.0.rst1182 - gallivm/nir: handle subgroup reduction across all types
1191 - gallivm/nir: fix subgroup invocation read.
2008 - intel/fs: Handle required subgroup sizes specified in the SPIR-V
2903 - zink: lower subgroup ballot instructions
2904 - zink: implement compiler handling for subgroup ballot builtins/intrinsics
3892 - radv: store the CS subgroup size to radv_shader_info
H A D20.1.0.rst3921 - radv/gfx10: fix required subgroup size with
3927 - radv: remove wrong assert that checks compute subgroup size
3937 - radv/llvm: fix subgroup shuffle for chips without bpermute
4003 - radv: adjust the supported subgroup stages
4196 - radv: Enable subgroup shuffle on GFX10 when ACO is used.
H A D20.2.0.rst3937 - aco: implement subgroup shader_clock on GFX10.3
4325 - aco: sign-extend the input and identity for 8-bit subgroup operations
4331 - ac/nir: fix shader clock with subgroup scope
4353 - aco: sign-extend input/identity for 16-bit subgroup ops on GFX6-GFX7
4356 - aco: fix sign-extend 8-bit subgroup operations on GFX6-GFX7
4632 - aco: Implement subgroup shuffle on GFX6-7.
4633 - radv/aco: Always enable subgroup shuffle.
H A D21.0.0.rst330 - pan/bi: Use canonical subgroup size
2781 - nir: gather whether a compute shader uses non-quad subgroup intrinsics
2783 - nir/load_store_vectorize: don't ignore subgroup memory barriers
H A D19.3.0.rst1780 - intel/fs: Do 8-bit subgroup scan operations in 16 bits
3313 - aco: Implement subgroup shuffle in GFX10 wave64 mode.
H A D19.1.0.rst120 - [BSW BXT GLK] dEQP-VK.subgroups.arithmetic.subgroup regressions
2344 - iris/compute: Push subgroup-id
H A D19.0.0.rst190 - [BSW BXT GLK] dEQP-VK.subgroups.arithmetic.subgroup regressions
/xsrc/external/mit/MesaLib/src/panfrost/bifrost/
H A Dbi_printer.c502 bi_subgroup_as_str(enum bi_subgroup subgroup) argument
504 switch (subgroup) {
510 unreachable("Invalid subgroup");
1380 fputs(bi_subgroup_as_str(I->subgroup), fp);
4733 fputs(bi_subgroup_as_str(I->subgroup), fp);
H A Dbi_builder.h969 bi_instr * bi_clper_i32_to(bi_builder *b, bi_index dest0, bi_index src0, bi_index src1, enum bi_inactive_result inactive_result, enum bi_lane_op lane_op, enum bi_subgroup subgroup) argument
977 I->subgroup = subgroup;
984 bi_index bi_clper_i32(bi_builder *b, bi_index src0, bi_index src1, enum bi_inactive_result inactive_result, enum bi_lane_op lane_op, enum bi_subgroup subgroup) argument
986 return (bi_clper_i32_to(b, bi_temp(b->shader), src0, src1, inactive_result, lane_op, subgroup))->dest[0];
6767 bi_instr * bi_wmask_to(bi_builder *b, bi_index dest0, bi_index src0, enum bi_subgroup subgroup, uint32_t fill) argument
6773 I->subgroup = subgroup;
6780 bi_index bi_wmask(bi_builder *b, bi_index src0, enum bi_subgroup subgroup, uint32_t fill) argument
6782 return (bi_wmask_to(b, bi_temp(b->shader), src0, subgroup, fil
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H A Dbi_packer.c2511 unsigned subgroup = I->subgroup; local in function:bi_pack_add_clper_i32
2512 assert(subgroup < 4);
2515 return 0x7c000 | (src0 << 0) | (src1 << 3) | (lane_op << 6) | (subgroup << 8) | (inactive_result << 10);
5710 unsigned subgroup = I->subgroup; local in function:bi_pack_add_wmask
5711 assert(subgroup < 4);
5714 return 0x3d700 | (src0 << 0) | (subgroup << 4) | (fill << 3);
H A Dbifrost_gen_disasm.c4457 const char *subgroup = subgroup_table[_BITS(bits, 8, 2)]; local in function:bi_disasm_add_clper_i32
4467 fputs(subgroup, fp);
10592 const char *subgroup = subgroup_table[_BITS(bits, 4, 2)]; local in function:bi_disasm_add_wmask
10595 fputs(subgroup, fp);
/xsrc/external/mit/MesaLib/dist/src/panfrost/bifrost/
H A Dcompiler.h457 enum bi_subgroup subgroup; /* WMASK, CLPER */ member in struct:__anon9a2e09910208::__anon9a2e0991060a::__anon9a2e09910c08
/xsrc/external/mit/MesaLib.old/dist/src/gallium/docs/source/
H A Dtgsi.rst2843 running in the current SIMD group. Every thread in the subgroup will receive
3420 This semantic indicates the subgroup size for the current invocation. This is
3428 The index of the current invocation within its subgroup.
/xsrc/external/mit/MesaLib/dist/docs/gallium/
H A Dtgsi.rst2907 running in the current SIMD group. Every thread in the subgroup will receive
3484 This semantic indicates the subgroup size for the current invocation. This is
3492 The index of the current invocation within its subgroup.
/xsrc/external/mit/MesaLib/dist/src/amd/llvm/
H A Dac_llvm_build.c471 const char *subgroup = "llvm.readcyclecounter"; local in function:ac_build_shader_clock
472 const char *name = scope == NIR_SCOPE_DEVICE ? "llvm.amdgcn.s.memrealtime" : subgroup;
/xsrc/external/mit/xorg-server.old/dist/hw/dmx/doc/
H A Ddoxygen.conf.in151 # subgroup of that type (e.g. under the Public Functions section). Set it to
/xsrc/external/mit/MesaLib/dist/
H A D.pick_status.json1633 "description": "pan/va: Make subgroup 4-bits",
6997 "description": "ir3,tu: Enable subgroup shuffles and relative shuffles",
23701 "description": "ir3,turnip: Enable subgroup ops support in all stages on gen4",
23719 "description": "ir3: Add gen4 new subgroup instructions",
26950 "description": "ir3/cp: Prevent setting an address on subgroup macros",
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