Searched refs:surface_count (Results 1 - 19 of 19) sorted by relevance

/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Dgfx7_cmd_buffer.c423 uint32_t surface_count = 0; local in function:genX
427 surface_count = map->surface_count;
441 for (uint32_t i = 0; i < surface_count; i++) {
458 GENX(BLEND_STATE_ENTRY_length) * surface_count;
H A Danv_nir_apply_pipeline_layout.c1438 map->surface_to_descriptor[map->surface_count] =
1443 state.set[s].desc_offset = map->surface_count;
1444 map->surface_count++;
1449 state.constants_offset = map->surface_count;
1450 map->surface_to_descriptor[map->surface_count].set =
1452 map->surface_count++;
1519 if (map->surface_count + array_size > MAX_BINDING_TABLE_SIZE ||
1528 state.set[set].surface_offsets[b] = map->surface_count;
1534 map->surface_to_descriptor[map->surface_count++] =
1544 map->surface_to_descriptor[map->surface_count
[all...]
H A Danv_pipeline_cache.c60 bind_map->surface_count);
143 bind_map->surface_count);
198 blob_write_uint32(blob, shader->bind_map.surface_count);
201 shader->bind_map.surface_count *
249 bind_map.surface_count = blob_read_uint32(blob);
252 blob_read_bytes(blob, bind_map.surface_count *
H A Dgfx8_cmd_buffer.c726 uint32_t surface_count = 0; local in function:genX
730 surface_count = map->surface_count;
744 for (uint32_t i = 0; i < surface_count; i++) {
761 GENX(BLEND_STATE_ENTRY_length) * surface_count;
H A DgenX_pipeline.c1220 uint32_t surface_count = 0; local in function:emit_cb_state
1224 surface_count = map->surface_count;
1228 GENX(BLEND_STATE_ENTRY_length) * surface_count;
1249 for (unsigned i = 0; i < surface_count; i++) {
1793 vs.BindingTableEntryCount = vs_bin->bind_map.surface_count;
1870 hs.BindingTableEntryCount = tcs_bin->bind_map.surface_count;
1952 ds.BindingTableEntryCount = tes_bin->bind_map.surface_count;
2015 gs.BindingTableEntryCount = gs_bin->bind_map.surface_count;
2076 for (int i = 0; i < bind_map->surface_count;
[all...]
H A Danv_descriptor_set.c256 uint32_t surface_count[MESA_VULKAN_SHADER_STAGES] = { 0, }; local in function:anv_GetDescriptorSetLayoutSupport
300 surface_count[s] += sampler->n_planes;
304 surface_count[s] += binding->descriptorCount;
313 surface_count[s] += binding->descriptorCount;
318 for (unsigned s = 0; s < ARRAY_SIZE(surface_count); s++) {
320 surface_count[s] += 1;
337 for (unsigned s = 0; s < ARRAY_SIZE(surface_count); s++) {
341 if (surface_count[s] > MAX_BINDING_TABLE_SIZE - MAX_RTS)
H A Danv_pipeline.c1116 assert(stage->bind_map.surface_count == 0);
1119 stage->bind_map.surface_count += num_rt_bindings;
1904 stage.bind_map.surface_count = 1;
3009 .surface_count = 0,
3062 .surface_count = 0,
H A DgenX_cmd_buffer.c2574 if (map->surface_count == 0) {
2580 map->surface_count,
2594 for (uint32_t s = 0; s < map->surface_count; s++) {
4900 1 + MIN2(pipeline->cs->bind_map.surface_count, 30),
H A Danv_blorp.c68 .surface_count = 0,
H A Danv_private.h3418 uint32_t surface_count; member in struct:anv_pipeline_bind_map
/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_nir_apply_pipeline_layout.c1133 map->surface_to_descriptor[map->surface_count] =
1138 state.set[s].desc_offset = map->surface_count;
1139 map->surface_count++;
1144 state.constants_offset = map->surface_count;
1145 map->surface_to_descriptor[map->surface_count].set =
1147 map->surface_count++;
1216 if (map->surface_count + array_size > MAX_BINDING_TABLE_SIZE ||
1224 state.set[set].surface_offsets[b] = map->surface_count;
1229 map->surface_to_descriptor[map->surface_count++] =
1239 assert(map->surface_count <
[all...]
H A Danv_pipeline_cache.c60 bind_map->surface_count);
107 bind_map->surface_count);
155 blob_write_uint32(blob, shader->bind_map.surface_count);
158 shader->bind_map.surface_count *
194 bind_map.surface_count = blob_read_uint32(blob);
197 blob_read_bytes(blob, bind_map.surface_count *
H A DgenX_pipeline.c909 uint32_t surface_count = 0; local in function:emit_cb_state
913 surface_count = map->surface_count;
917 GENX(BLEND_STATE_ENTRY_length) * surface_count;
927 for (unsigned i = 0; i < surface_count; i++) {
1295 return DIV_ROUND_UP(bin->bind_map.surface_count, 32);
1588 for (int i = 0; i < bind_map->surface_count; i++) {
2122 * for in bind_map.surface_count.
2124 .BindingTableEntryCount = GEN_GEN == 11 ? 0 : 1 + MIN2(cs_bin->bind_map.surface_count, 30),
H A Danv_descriptor_set.c241 uint32_t surface_count[MESA_SHADER_STAGES] = { 0, }; local in function:anv_GetDescriptorSetLayoutSupport
263 surface_count[s] += sampler->n_planes;
267 surface_count[s] += binding->descriptorCount;
276 surface_count[s] += binding->descriptorCount;
286 if (surface_count[s] >= MAX_BINDING_TABLE_SIZE - MAX_RTS)
H A Danv_pipeline.c918 assert(stage->bind_map.surface_count == 0);
921 stage->bind_map.surface_count += num_rts;
1323 stage.bind_map.surface_count = 1;
H A DgenX_cmd_buffer.c2055 if (map->surface_count == 0) {
2061 map->surface_count,
2074 for (uint32_t s = 0; s < map->surface_count; s++) {
2496 assert(surface <= bind_map->surface_count);
H A Danv_blorp.c68 .surface_count = 0,
H A Danv_private.h2679 uint32_t surface_count; member in struct:anv_pipeline_bind_map
/xsrc/external/mit/xf86-video-qxl/dist/src/
H A Dqxl_surface_ums.c109 static int surface_count(qxl_surface_t *surface) function in typeref:typename:int
122 live_n = surface_count(cache->live_surfaces);
123 free_n = surface_count(cache->free_surfaces);

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