Searched refs:surface_to_descriptor (Results 1 - 15 of 15) sorted by relevance

/xsrc/external/mit/MesaLib.old/dist/src/intel/vulkan/
H A Danv_pipeline_cache.c48 struct anv_pipeline_binding *surface_to_descriptor, *sampler_to_descriptor; local in function:anv_shader_bin_create
59 anv_multialloc_add(&ma, &surface_to_descriptor,
106 typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
108 shader->bind_map.surface_to_descriptor = surface_to_descriptor;
157 blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
159 sizeof(*shader->bind_map.surface_to_descriptor));
196 bind_map.surface_to_descriptor = (void *)
198 sizeof(*bind_map.surface_to_descriptor));
[all...]
H A Danv_pipeline.c439 struct anv_pipeline_binding surface_to_descriptor[256]; member in struct:anv_pipeline_stage
919 typed_memcpy(stage->bind_map.surface_to_descriptor,
1111 .surface_to_descriptor = stages[s].surface_to_descriptor,
1318 .surface_to_descriptor = stage.surface_to_descriptor,
1324 stage.bind_map.surface_to_descriptor[0] = (struct anv_pipeline_binding) {
H A Danv_nir_apply_pipeline_layout.c1133 map->surface_to_descriptor[map->surface_count] =
1145 map->surface_to_descriptor[map->surface_count].set =
1229 map->surface_to_descriptor[map->surface_count++] =
1303 &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
H A DgenX_pipeline.c928 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
1589 struct anv_pipeline_binding *binding = &bind_map->surface_to_descriptor[i];
H A Danv_private.h2682 struct anv_pipeline_binding * surface_to_descriptor; member in struct:anv_pipeline_bind_map
H A DgenX_cmd_buffer.c2075 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
2498 &bind_map->surface_to_descriptor[surface];
/xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
H A Danv_pipeline_cache.c59 VK_MULTIALLOC_DECL(&ma, struct anv_pipeline_binding, surface_to_descriptor,
142 typed_memcpy(surface_to_descriptor, bind_map->surface_to_descriptor,
144 shader->bind_map.surface_to_descriptor = surface_to_descriptor;
200 blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
202 sizeof(*shader->bind_map.surface_to_descriptor));
251 bind_map.surface_to_descriptor = (void *)
253 sizeof(*bind_map.surface_to_descriptor));
H A Danv_nir_compute_push_layout.c232 &map->surface_to_descriptor[ubo_range->block];
H A Danv_nir_apply_pipeline_layout.c1438 map->surface_to_descriptor[map->surface_count] =
1450 map->surface_to_descriptor[map->surface_count].set =
1534 map->surface_to_descriptor[map->surface_count++] =
1544 map->surface_to_descriptor[map->surface_count++] =
1610 &map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
1680 _mesa_sha1_compute(map->surface_to_descriptor,
H A Danv_pipeline.c606 struct anv_pipeline_binding surface_to_descriptor[256]; member in struct:anv_pipeline_stage
1117 typed_memcpy(stage->bind_map.surface_to_descriptor,
1607 .surface_to_descriptor = stages[s].surface_to_descriptor,
1899 .surface_to_descriptor = stage.surface_to_descriptor,
1905 stage.bind_map.surface_to_descriptor[0] = (struct anv_pipeline_binding) {
1940 assert(stage.bind_map.surface_to_descriptor[0].set ==
1942 stage.bind_map.surface_to_descriptor[0].set = ANV_DESCRIPTOR_SET_NULL;
H A Dgfx7_cmd_buffer.c442 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
H A Dgfx8_cmd_buffer.c745 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
H A DgenX_pipeline.c1250 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[i];
2077 struct anv_pipeline_binding *binding = &bind_map->surface_to_descriptor[i];
H A Danv_private.h3421 struct anv_pipeline_binding * surface_to_descriptor; member in struct:anv_pipeline_bind_map
H A DgenX_cmd_buffer.c2595 struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];

Completed in 67 milliseconds