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    Searched refs:tiling_flags (Results 1 - 25 of 59) sorted by relevancy

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  /xsrc/external/mit/xf86-video-ati-kms/dist/src/
radeon_bo_helper.c 112 int width, int height, int cpp, uint32_t tiling_flags,
133 tiling_flags &= ~RADEON_TILING_MACRO;
144 if ((tiling_flags & RADEON_TILING_MACRO)) {
147 } else if ((tiling_flags & RADEON_TILING_MICRO)) {
154 surface->bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) &
156 surface->bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) &
158 surface->tile_split = eg_tile_split_opp((tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) &
162 (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
165 surface->mtilea = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
404 priv->tiling_flags = args.tiling_flags
517 uint32_t tiling_flags; local
    [all...]
radeon_exa.c 183 if (driver_priv->tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
262 &new_priv->tiling_flags);
312 return driver_priv->tiling_flags;
evergreen_textured_videofuncs.c 144 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
155 src_obj.tiling_flags = 0;
249 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
283 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
307 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
348 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
404 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
r600_textured_videofuncs.c 156 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
167 src_obj.tiling_flags = 0;
266 if (accel_state->src_obj[0].tiling_flags == 0)
299 if (accel_state->src_obj[0].tiling_flags == 0)
322 if (accel_state->src_obj[0].tiling_flags == 0)
362 if (accel_state->src_obj[0].tiling_flags == 0)
418 if (accel_state->dst_obj.tiling_flags == 0)
evergreen_exa.c 75 dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
159 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
339 if ((accel_state->src_obj[0].tiling_flags & RADEON_TILING_MASK) ==
383 if ((accel_state->dst_obj.tiling_flags & RADEON_TILING_MASK) ==
473 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
474 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
501 drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
589 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
590 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
599 accel_state->dst_obj.tiling_flags = 0
    [all...]
r600_exa.c 96 accel_state->dst_obj.tiling_flags = 0;
154 dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
237 if (accel_state->dst_obj.tiling_flags == 0)
410 if (accel_state->src_obj[0].tiling_flags == 0)
454 if (accel_state->dst_obj.tiling_flags == 0)
539 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
540 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
654 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
655 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
662 accel_state->dst_obj.tiling_flags = 0
    [all...]
radeon_present.c 203 uint32_t tiling_flags = radeon_get_pixmap_tiling_flags(pixmap); local
208 if ((tiling_flags & RADEON_TILING_MACRO) &&
210 tiling_flags &= ~RADEON_TILING_MICRO;
212 return tiling_flags;
  /xsrc/external/mit/libdrm/dist/radeon/
radeon_bo.h 67 int radeon_bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch);
68 int radeon_bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags, uint32_t *pitch);
radeon_bo_int.h 37 int (*bo_set_tiling)(struct radeon_bo_int *bo, uint32_t tiling_flags,
39 int (*bo_get_tiling)(struct radeon_bo_int *bo, uint32_t *tiling_flags,
radeon_bo.c 98 uint32_t tiling_flags, uint32_t pitch)
101 return boi->bom->funcs->bo_set_tiling(boi, tiling_flags, pitch);
106 uint32_t *tiling_flags, uint32_t *pitch)
109 return boi->bom->funcs->bo_get_tiling(boi, tiling_flags, pitch);
radeon_bo_gem.c 227 static int bo_set_tiling(struct radeon_bo_int *boi, uint32_t tiling_flags,
234 args.tiling_flags = tiling_flags;
244 static int bo_get_tiling(struct radeon_bo_int *boi, uint32_t *tiling_flags,
261 *tiling_flags = args.tiling_flags;
  /xsrc/external/mit/MesaLib.old/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 659 uint32_t tiling_flags = 0; local
662 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
665 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
667 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
669 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
671 tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, md->u.legacy.pipe_config);
672 tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(md->u.legacy.bankw));
673 tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(md->u.legacy.bankh));
675 tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, radv_eg_tile_split_rev(md->u.legacy.tile_split));
676 tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(md->u.legacy.mtilea))
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/winsys/amdgpu/
radv_amdgpu_bo.c 913 uint64_t tiling_flags = 0; local
916 tiling_flags |= AMDGPU_TILING_SET(SWIZZLE_MODE, md->u.gfx9.swizzle_mode);
917 tiling_flags |= AMDGPU_TILING_SET(DCC_OFFSET_256B, md->u.gfx9.dcc_offset_256b);
918 tiling_flags |= AMDGPU_TILING_SET(DCC_PITCH_MAX, md->u.gfx9.dcc_pitch_max);
919 tiling_flags |= AMDGPU_TILING_SET(DCC_INDEPENDENT_64B, md->u.gfx9.dcc_independent_64b_blocks);
920 tiling_flags |=
922 tiling_flags |=
924 tiling_flags |= AMDGPU_TILING_SET(SCANOUT, md->u.gfx9.scanout);
927 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
929 tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 *
    [all...]
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/amdgpu/drm/
amdgpu_bo.c 1218 uint64_t tiling_flags; local
1227 tiling_flags = info.metadata.tiling_info;
1230 md->u.gfx9.swizzle_mode = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
1232 md->u.gfx9.dcc_offset_256B = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
1233 md->u.gfx9.dcc_pitch_max = AMDGPU_TILING_GET(tiling_flags, DCC_PITCH_MAX);
1234 md->u.gfx9.dcc_independent_64B = AMDGPU_TILING_GET(tiling_flags, DCC_INDEPENDENT_64B);
1239 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
1241 else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /* 1D_TILED_THIN1 */
1244 md->u.legacy.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1245 md->u.legacy.bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH)
1262 uint64_t tiling_flags = 0; local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/gallium/winsys/radeon/drm/
radeon_drm_bo.c 897 if (args.tiling_flags & RADEON_TILING_MACRO)
899 else if (args.tiling_flags & RADEON_TILING_MICRO)
904 surf->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
905 surf->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
906 surf->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
908 surf->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
910 if (bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT))
919 if (args.tiling_flags & RADEON_TILING_MICRO)
921 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
924 if (args.tiling_flags & RADEON_TILING_MACRO
    [all...]
  /xsrc/external/mit/xf86-video-ati/dist/src/
radeon_kms.c 1233 uint32_t tiling_flags = 0; local
1251 tiling_flags |= RADEON_TILING_MACRO;
1253 tiling_flags |= RADEON_TILING_MICRO;
1256 tiling_flags |= RADEON_TILING_MACRO;
1258 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, tiling_flags)) * cpp;
1259 screen_size = RADEON_ALIGN(pScrn->virtualY, drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
1260 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
1281 if (tiling_flags & RADEON_TILING_MICRO) {
1285 if (tiling_flags & RADEON_TILING_MACRO) {
1302 tiling_flags = 0
    [all...]
drmmode_display.c 246 uint32_t tiling_flags = 0; local
269 tiling_flags |= RADEON_TILING_MACRO;
271 tiling_flags |= RADEON_TILING_MICRO;
274 tiling_flags |= RADEON_TILING_MACRO;
278 drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
284 tiling_flags, info->front_bo, &info->front_surface);
333 uint32_t tiling_flags = 0; local
338 tiling_flags |= RADEON_TILING_MICRO;
340 tiling_flags |= RADEON_TILING_MACRO;
343 pitch = RADEON_ALIGN(pScrn->displayWidth, drmmode_get_pitch_align(pScrn, info->CurrentLayout.pixel_bytes, tiling_flags)) *
1269 uint32_t tiling_flags = 0, base_align; local
1794 uint32_t tiling_flags = 0; local
    [all...]
evergreen_textured_videofuncs.c 160 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
171 src_obj.tiling_flags = 0;
265 if (accel_state->src_obj[0].tiling_flags == 0)
298 if (accel_state->src_obj[0].tiling_flags == 0)
321 if (accel_state->src_obj[0].tiling_flags == 0)
361 if (accel_state->src_obj[0].tiling_flags == 0)
416 if (accel_state->dst_obj.tiling_flags == 0) {
r600_textured_videofuncs.c 172 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pPixmap);
189 src_obj.tiling_flags = 0;
293 if (accel_state->src_obj[0].tiling_flags == 0)
326 if (accel_state->src_obj[0].tiling_flags == 0)
349 if (accel_state->src_obj[0].tiling_flags == 0)
389 if (accel_state->src_obj[0].tiling_flags == 0)
448 if (accel_state->dst_obj.tiling_flags == 0)
evergreen_exa.c 79 dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
163 if (accel_state->dst_obj.tiling_flags == 0) {
342 if (accel_state->src_obj[0].tiling_flags == 0)
385 if (accel_state->dst_obj.tiling_flags == 0) {
476 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
477 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
501 drmmode_get_height_align(pScrn, accel_state->dst_obj.tiling_flags));
584 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
585 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
595 accel_state->dst_obj.tiling_flags = 0
    [all...]
r600_exa.c 113 accel_state->dst_obj.tiling_flags = 0;
189 dst.tiling_flags = radeon_get_pixmap_tiling(pPix);
281 if (accel_state->dst_obj.tiling_flags == 0)
459 if (accel_state->src_obj[0].tiling_flags == 0)
506 if (accel_state->dst_obj.tiling_flags == 0)
595 dst_obj.tiling_flags = radeon_get_pixmap_tiling(pDst);
596 src_obj.tiling_flags = radeon_get_pixmap_tiling(pSrc);
733 uint32_t orig_src_tiling_flags = accel_state->src_obj[0].tiling_flags;
734 uint32_t orig_dst_tiling_flags = accel_state->dst_obj.tiling_flags;
753 accel_state->dst_obj.tiling_flags = 0
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/isl/tests/
isl_surf_get_image_offset_test.c 145 .tiling_flags = ISL_TILING_Y0_BIT);
193 .tiling_flags = ISL_TILING_Y0_BIT);
254 .tiling_flags = ISL_TILING_Y0_BIT);
  /xsrc/external/mit/MesaLib.old/dist/src/intel/isl/tests/
isl_surf_get_image_offset_test.c 145 .tiling_flags = ISL_TILING_Y0_BIT);
193 .tiling_flags = ISL_TILING_Y0_BIT);
254 .tiling_flags = ISL_TILING_Y0_BIT);
  /xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
brw_tex.c 360 isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
362 tiling_flags = ISL_TILING_LINEAR_BIT;
375 .tiling_flags = tiling_flags);
  /xsrc/external/mit/MesaLib.old/dist/src/gallium/winsys/radeon/drm/
radeon_drm_bo.c 894 if (args.tiling_flags & RADEON_TILING_MICRO)
896 else if (args.tiling_flags & RADEON_TILING_MICRO_SQUARE)
899 if (args.tiling_flags & RADEON_TILING_MACRO)
902 md->u.legacy.bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
903 md->u.legacy.bankh = (args.tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
904 md->u.legacy.tile_split = (args.tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
905 md->u.legacy.mtilea = (args.tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
907 md->u.legacy.scanout = bo->rws->gen >= DRV_SI && !(args.tiling_flags & RADEON_TILING_R600_NO_SCANOUT);
923 args.tiling_flags |= RADEON_TILING_MICRO;
925 args.tiling_flags |= RADEON_TILING_MICRO_SQUARE
    [all...]

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