Searched refs:vtbl (Results 1 - 25 of 182) sorted by relevance

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/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/iris/
H A Diris_perf.c48 batch->screen->vtbl.emit_mi_report_perf_count(batch, bo, offset_in_bytes, report_id);
66 batch->screen->vtbl.store_register_mem64(batch, reg, bo, offset, false);
69 batch->screen->vtbl.store_register_mem32(batch, reg, bo, offset, false);
88 perf_cfg->vtbl.bo_alloc = iris_oa_bo_alloc;
89 perf_cfg->vtbl.bo_unreference = (bo_unreference_t)iris_bo_unreference;
90 perf_cfg->vtbl.bo_map = (bo_map_t)iris_bo_map;
91 perf_cfg->vtbl.bo_unmap = (bo_unmap_t)iris_bo_unmap;
92 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard =
95 perf_cfg->vtbl.emit_mi_report_perf_count =
97 perf_cfg->vtbl
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i965/
H A Dbrw_pipe_control.c59 brw->vtbl.emit_raw_pipe_control(brw, flags, NULL, 0, 0);
75 brw->vtbl.emit_raw_pipe_control(brw, flags, bo, offset, imm);
170 brw->vtbl.emit_raw_pipe_control(brw,
174 brw->vtbl.emit_raw_pipe_control(brw,
376 brw->vtbl.emit_raw_pipe_control = gen11_emit_raw_pipe_control;
379 brw->vtbl.emit_raw_pipe_control = gen10_emit_raw_pipe_control;
382 brw->vtbl.emit_raw_pipe_control = gen9_emit_raw_pipe_control;
385 brw->vtbl.emit_raw_pipe_control = gen8_emit_raw_pipe_control;
388 brw->vtbl.emit_raw_pipe_control =
393 brw->vtbl
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/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i965/
H A Dbrw_pipe_control.c59 brw->vtbl.emit_raw_pipe_control(brw, flags, NULL, 0, 0);
75 brw->vtbl.emit_raw_pipe_control(brw, flags, bo, offset, imm);
171 brw->vtbl.emit_raw_pipe_control(brw,
175 brw->vtbl.emit_raw_pipe_control(brw,
401 brw->vtbl.emit_raw_pipe_control = gfx11_emit_raw_pipe_control;
404 brw->vtbl.emit_raw_pipe_control = gfx9_emit_raw_pipe_control;
407 brw->vtbl.emit_raw_pipe_control = gfx8_emit_raw_pipe_control;
410 brw->vtbl.emit_raw_pipe_control =
415 brw->vtbl.emit_raw_pipe_control = gfx6_emit_raw_pipe_control;
418 brw->vtbl
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H A Dbrw_performance_query.c431 ctx->vtbl.emit_mi_report_perf_count(ctx,
494 perf_cfg->vtbl.bo_alloc = brw_oa_bo_alloc;
495 perf_cfg->vtbl.bo_unreference = (bo_unreference_t)brw_bo_unreference;
496 perf_cfg->vtbl.bo_map = (bo_map_t)brw_bo_map;
497 perf_cfg->vtbl.bo_unmap = (bo_unmap_t)brw_bo_unmap;
498 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard =
500 perf_cfg->vtbl.emit_mi_report_perf_count =
502 perf_cfg->vtbl.batchbuffer_flush = brw_oa_batchbuffer_flush;
503 perf_cfg->vtbl.store_register_mem =
505 perf_cfg->vtbl
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/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/i915/
H A Dintel_buffers.h45 intel->vtbl.update_draw_buffer(intel);
H A Dintel_batchbuffer.c106 if (intel->vtbl.debug_batch != NULL)
107 intel->vtbl.debug_batch(intel);
123 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub)
124 intel->vtbl.annotate_aub(intel);
137 intel->vtbl.new_batch(intel);
162 if (intel->vtbl.finish_batch)
163 intel->vtbl.finish_batch(intel);
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/i915/
H A Dintel_buffers.h45 intel->vtbl.update_draw_buffer(intel);
H A Dintel_batchbuffer.c106 if (intel->vtbl.debug_batch != NULL)
107 intel->vtbl.debug_batch(intel);
123 if (unlikely(INTEL_DEBUG & DEBUG_AUB) && intel->vtbl.annotate_aub)
124 intel->vtbl.annotate_aub(intel);
137 intel->vtbl.new_batch(intel);
162 if (intel->vtbl.finish_batch)
163 intel->vtbl.finish_batch(intel);
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/pipebuffer/
H A Dpb_buffer.h118 const struct pb_vtbl *vtbl; member in struct:pb_buffer
165 /* Accessor functions for pb->vtbl:
174 return buf->vtbl->map(buf, flags, flush_ctx);
185 buf->vtbl->unmap(buf);
201 assert(buf->vtbl->get_base_buffer);
202 buf->vtbl->get_base_buffer(buf, base_buf, offset);
215 assert(buf->vtbl->validate);
216 return buf->vtbl->validate(buf, vl, flags);
226 assert(buf->vtbl->fence);
227 buf->vtbl
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/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/pipebuffer/
H A Dpb_buffer.h139 const struct pb_vtbl *vtbl; member in struct:pb_buffer
186 /* Accessor functions for pb->vtbl:
195 return buf->vtbl->map(buf, flags, flush_ctx);
206 buf->vtbl->unmap(buf);
222 assert(buf->vtbl->get_base_buffer);
223 buf->vtbl->get_base_buffer(buf, base_buf, offset);
236 assert(buf->vtbl->validate);
237 return buf->vtbl->validate(buf, vl, flags);
247 assert(buf->vtbl->fence);
248 buf->vtbl
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/xsrc/external/mit/MesaLib/dist/src/gallium/auxiliary/util/
H A Du_transfer_helper.c35 const struct u_transfer_vtbl *vtbl; member in struct:u_transfer_helper
46 if (helper->vtbl->get_internal_format) {
48 helper->vtbl->get_internal_format(prsc);
67 * helper->vtbl fxns directly, but calls back to pctx->transfer_map()/etc
99 prsc = helper->vtbl->resource_create(pscreen, &t);
106 stencil = helper->vtbl->resource_create(pscreen, &t);
109 helper->vtbl->resource_destroy(pscreen, prsc);
113 helper->vtbl->set_stencil(prsc, stencil);
119 prsc = helper->vtbl->resource_create(pscreen, &t);
126 prsc = helper->vtbl
526 u_transfer_helper_create(const struct u_transfer_vtbl * vtbl,bool separate_z32s8,bool separate_stencil,bool fake_rgtc,bool msaa_map) argument
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/xsrc/external/mit/MesaLib/dist/include/android_stub/hardware/
H A Dhwvulkan.h40 * the 'vtbl' field.
51 const void* vtbl; member in union:__anon376d5fa8010a
/xsrc/external/mit/MesaLib.old/dist/src/gallium/auxiliary/util/
H A Du_transfer_helper.c35 const struct u_transfer_vtbl *vtbl; member in struct:u_transfer_helper
46 if (helper->vtbl->get_internal_format) {
48 helper->vtbl->get_internal_format(prsc);
67 * helper->vtbl fxns directly, but calls back to pctx->transfer_map()/etc
99 prsc = helper->vtbl->resource_create(pscreen, &t);
106 stencil = helper->vtbl->resource_create(pscreen, &t);
109 helper->vtbl->resource_destroy(pscreen, prsc);
113 helper->vtbl->set_stencil(prsc, stencil);
119 prsc = helper->vtbl->resource_create(pscreen, &t);
126 prsc = helper->vtbl
521 u_transfer_helper_create(const struct u_transfer_vtbl * vtbl,bool separate_z32s8,bool separate_stencil,bool fake_rgtc,bool msaa_map) argument
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H A Du_transfer.c120 return ur->vtbl->resource_get_handle(screen, resource, handle);
127 ur->vtbl->resource_destroy(screen, resource);
138 return ur->vtbl->transfer_map(context, resource, level, usage, box,
147 ur->vtbl->transfer_flush_region(pipe, transfer, box);
154 ur->vtbl->transfer_unmap(pipe, transfer);
/xsrc/external/mit/xf86-video-sis/dist/src/
H A DMakefile.am32 300vtbl.h \
33 310vtbl.h \
/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/i915/
H A Di915_resource.h100 assert(tex->b.vtbl == &i915_texture_vtbl);
107 assert(tex->b.vtbl == &i915_buffer_vtbl);
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/panfrost/
H A Dpan_assemble.c80 screen->vtbl.compile_shader(s, &inputs, &binary, &state->info);
92 screen->vtbl.prepare_rsd(state, desc_pool, upload);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_context.c126 radeon->vtbl.swtcl_flush = r100_swtcl_flush;
127 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
128 radeon->vtbl.fallback = radeonFallback;
129 radeon->vtbl.free_context = r100_vtbl_free_context;
130 radeon->vtbl.emit_query_finish = r100_emit_query_finish;
131 radeon->vtbl.check_blit = r100_check_blit;
132 radeon->vtbl.blit = r100_blit;
133 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
134 radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers;
/xsrc/external/mit/MesaLib/dist/src/mesa/drivers/dri/radeon/
H A Dradeon_context.c126 radeon->vtbl.swtcl_flush = r100_swtcl_flush;
127 radeon->vtbl.pre_emit_state = r100_vtbl_pre_emit_state;
128 radeon->vtbl.fallback = radeonFallback;
129 radeon->vtbl.free_context = r100_vtbl_free_context;
130 radeon->vtbl.emit_query_finish = r100_emit_query_finish;
131 radeon->vtbl.check_blit = r100_check_blit;
132 radeon->vtbl.blit = r100_blit;
133 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
134 radeon->vtbl.revalidate_all_buffers = r100ValidateBuffers;
/xsrc/external/mit/MesaLib/dist/src/gallium/drivers/crocus/
H A Dcrocus_monitor.c144 screen->vtbl.emit_mi_report_perf_count(batch, bo, offset_in_bytes, report_id);
162 ice->vtbl.store_register_mem32(batch, GEN9_RPSTAT0, bo, bo_offset, false);
171 ice->vtbl.store_register_mem64(batch, reg, bo, offset, false);
189 perf_cfg->vtbl.bo_alloc = crocus_oa_bo_alloc;
190 perf_cfg->vtbl.bo_unreference = (bo_unreference_t)crocus_bo_unreference;
191 perf_cfg->vtbl.bo_map = (bo_map_t)crocus_bo_map;
192 perf_cfg->vtbl.bo_unmap = (bo_unmap_t)crocus_bo_unmap;
194 perf_cfg->vtbl.emit_mi_report_perf_count =
196 perf_cfg->vtbl.batchbuffer_flush = crocus_monitor_batchbuffer_flush;
197 perf_cfg->vtbl
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/xsrc/external/mit/MesaLib/dist/src/intel/perf/
H A Dintel_perf_query.c723 perf->vtbl.store_register_mem(ctx->ctx, obj->pipeline_stats.bo,
744 perf_cfg->vtbl.emit_mi_report_perf_count(perf_ctx->ctx, query->oa.bo,
753 perf_cfg->vtbl.store_register_mem(perf_ctx->ctx, query->oa.bo,
808 perf_cfg->vtbl.emit_stall_at_pixel_scoreboard(perf_ctx->ctx);
852 perf_cfg->vtbl.bo_unreference(query->oa.bo);
856 query->oa.bo = perf_cfg->vtbl.bo_alloc(perf_ctx->bufmgr,
861 void *map = perf_cfg->vtbl.bo_map(perf_ctx->ctx, query->oa.bo, MAP_WRITE);
863 perf_cfg->vtbl.bo_unmap(query->oa.bo);
899 perf_cfg->vtbl.bo_unreference(query->pipeline_stats.bo);
904 perf_cfg->vtbl
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/xsrc/external/mit/MesaLib.old/dist/src/gallium/drivers/iris/
H A Diris_query.c98 #define emit_lri32 ice->vtbl.load_register_imm32
99 #define emit_lri64 ice->vtbl.load_register_imm64
100 #define emit_lrr32 ice->vtbl.load_register_reg32
171 ice->vtbl.store_data_imm64(batch, bo, offset, true);
235 ice->vtbl.store_register_mem64(batch,
241 ice->vtbl.store_register_mem64(batch,
261 ice->vtbl.store_register_mem64(batch, reg, bo, offset, false);
286 ice->vtbl.store_register_mem64(batch, SO_NUM_PRIMS_WRITTEN(s),
288 ice->vtbl.store_register_mem64(batch, SO_PRIM_STORAGE_NEEDED(s),
523 ice->vtbl
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H A Diris_pipe_control.c77 batch->vtbl->emit_raw_pipe_control(batch, flags, NULL, 0, 0);
93 batch->vtbl->emit_raw_pipe_control(batch, flags, bo, offset, imm);
/xsrc/external/mit/MesaLib.old/dist/src/egl/drivers/dri2/
H A Degl_dri2_fallbacks.h65 dri2_dpy->vtbl->set_damage_region(drv, disp, surf, rects, n_rects);
66 return dri2_dpy->vtbl->swap_buffers(drv, disp, surf);
/xsrc/external/mit/MesaLib.old/dist/src/mesa/drivers/dri/r200/
H A Dr200_context.c161 radeon->vtbl.swtcl_flush = r200_swtcl_flush;
162 radeon->vtbl.fallback = r200Fallback;
163 radeon->vtbl.update_scissor = r200_vtbl_update_scissor;
164 radeon->vtbl.emit_query_finish = r200_emit_query_finish;
165 radeon->vtbl.check_blit = r200_check_blit;
166 radeon->vtbl.blit = r200_blit;
167 radeon->vtbl.is_format_renderable = radeonIsFormatRenderable;
168 radeon->vtbl.revalidate_all_buffers = r200ValidateBuffers;

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