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Searched defs:clk_activity_offset (Results 1 - 8 of 8) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c	2779 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:ci_update_dpm_settings 2794 clk_activity_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i) 2796 offset = clk_activity_offset & ~0x3; 2798 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2829 clk_activity_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i) 2831 offset = clk_activity_offset & ~0x3; 2833 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_fiji_smumgr.c	2568 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:fiji_update_dpm_settings 2583 clk_activity_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i) 2585 offset = clk_activity_offset & ~0x3; 2587 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2618 clk_activity_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i) 2620 offset = clk_activity_offset & ~0x3; 2622 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_polaris10_smumgr.c	2484 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:polaris10_update_dpm_settings 2499 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i) 2501 offset = clk_activity_offset & ~0x3; 2503 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2534 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i) 2536 offset = clk_activity_offset & ~0x3; 2538 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_tonga_smumgr.c	3167 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:tonga_update_dpm_settings 3182 clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i) 3184 offset = clk_activity_offset & ~0x3; 3186 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 3217 clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i) 3219 offset = clk_activity_offset & ~0x3; 3221 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_ci_smumgr.c	2779 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:ci_update_dpm_settings 2794 clk_activity_offset = array + (sizeof(SMU7_Discrete_GraphicsLevel) * i) 2796 offset = clk_activity_offset & ~0x3; 2798 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2829 clk_activity_offset = mclk_array + (sizeof(SMU7_Discrete_MemoryLevel) * i) 2831 offset = clk_activity_offset & ~0x3; 2833 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_fiji_smumgr.c	2568 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:fiji_update_dpm_settings 2583 clk_activity_offset = array + (sizeof(SMU73_Discrete_GraphicsLevel) * i) 2585 offset = clk_activity_offset & ~0x3; 2587 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2618 clk_activity_offset = mclk_array + (sizeof(SMU73_Discrete_MemoryLevel) * i) 2620 offset = clk_activity_offset & ~0x3; 2622 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_polaris10_smumgr.c	2484 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:polaris10_update_dpm_settings 2499 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i) 2501 offset = clk_activity_offset & ~0x3; 2503 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 2534 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i) 2536 offset = clk_activity_offset & ~0x3; 2538 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
amdgpu_tonga_smumgr.c	3167 uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp; local in function:tonga_update_dpm_settings 3182 clk_activity_offset = array + (sizeof(SMU72_Discrete_GraphicsLevel) * i) 3184 offset = clk_activity_offset & ~0x3; 3186 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t)); 3217 clk_activity_offset = mclk_array + (sizeof(SMU72_Discrete_MemoryLevel) * i) 3219 offset = clk_activity_offset & ~0x3; 3221 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));

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