/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/ |
pxa25x.dtsi | 21 clks: pxa2xx_clks@41300004 { label 61 clocks = <&clks CLK_NONE>; 68 clocks = <&clks CLK_PWM0>; 75 clocks = <&clks CLK_PWM1>; 79 clocks = <&clks CLK_OSC32k768>;
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pxa25x.dtsi | 21 clks: pxa2xx_clks@41300004 { label 61 clocks = <&clks CLK_NONE>; 68 clocks = <&clks CLK_PWM0>; 75 clocks = <&clks CLK_PWM1>; 79 clocks = <&clks CLK_OSC32k768>;
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axm55xx.dtsi | 9 #include <dt-bindings/clock/lsi,axm5516-clks.h> 48 clks: clock-controller@2010020000 { label 49 compatible = "lsi,axm5516-clks"; 115 clocks = <&clks AXXIA_CLK_PER>; 124 clocks = <&clks AXXIA_CLK_PER>; 133 clocks = <&clks AXXIA_CLK_PER>; 142 clocks = <&clks AXXIA_CLK_PER>; 159 clocks = <&clks AXXIA_CLK_PER>; 177 clocks = <&clks AXXIA_CLK_PER>; 188 clocks = <&clks AXXIA_CLK_PER> [all...] |
pxa27x.dtsi | 35 clocks = <&clks CLK_NONE>; 42 clocks = <&clks CLK_USBHOST>; 50 clocks = <&clks CLK_PWM0>; 57 clocks = <&clks CLK_PWM1>; 64 clocks = <&clks CLK_PWM0>; 71 clocks = <&clks CLK_PWM1>; 78 clocks = <&clks CLK_PWRI2C>; 88 clocks = <&clks CLK_USB>; 96 clocks = <&clks CLK_KEYPAD>; 109 clocks = <&clks CLK_CAMERA> 131 clks: pxa2xx_clks@41300004 { label [all...] |
axm55xx.dtsi | 9 #include <dt-bindings/clock/lsi,axm5516-clks.h> 48 clks: clock-controller@2010020000 { label 49 compatible = "lsi,axm5516-clks"; 115 clocks = <&clks AXXIA_CLK_PER>; 124 clocks = <&clks AXXIA_CLK_PER>; 133 clocks = <&clks AXXIA_CLK_PER>; 142 clocks = <&clks AXXIA_CLK_PER>; 159 clocks = <&clks AXXIA_CLK_PER>; 177 clocks = <&clks AXXIA_CLK_PER>; 188 clocks = <&clks AXXIA_CLK_PER> [all...] |
pxa27x.dtsi | 35 clocks = <&clks CLK_NONE>; 42 clocks = <&clks CLK_USBHOST>; 50 clocks = <&clks CLK_PWM0>; 57 clocks = <&clks CLK_PWM1>; 64 clocks = <&clks CLK_PWM0>; 71 clocks = <&clks CLK_PWM1>; 78 clocks = <&clks CLK_PWRI2C>; 88 clocks = <&clks CLK_USB>; 96 clocks = <&clks CLK_KEYPAD>; 109 clocks = <&clks CLK_CAMERA> 131 clks: pxa2xx_clks@41300004 { label [all...] |
ep7209.dtsi | 44 clks: clks@80000000 { label 95 clocks = <&clks CLPS711X_CLK_BUS>; 112 clocks = <&clks CLPS711X_CLK_BUS>; 120 clocks = <&clks CLPS711X_CLK_TIMER1>; 127 clocks = <&clks CLPS711X_CLK_TIMER2>; 134 clocks = <&clks CLPS711X_CLK_PWM>; 142 clocks = <&clks CLPS711X_CLK_UART>; 152 clocks = <&clks CLPS711X_CLK_SPI>; 166 clocks = <&clks CLPS711X_CLK_UART> [all...] |
imx1.dtsi | 51 clocks = <&clks IMX1_CLK_MCU>; 82 clocks = <&clks IMX1_CLK_HCLK>, 83 <&clks IMX1_CLK_PER1>; 91 clocks = <&clks IMX1_CLK_HCLK>, 92 <&clks IMX1_CLK_PER1>; 100 clocks = <&clks IMX1_CLK_DUMMY>, 101 <&clks IMX1_CLK_DUMMY>, 102 <&clks IMX1_CLK_PER2>; 111 clocks = <&clks IMX1_CLK_HCLK>, 112 <&clks IMX1_CLK_PER1> 199 clks: ccm@21b000 { label [all...] |
ep7209.dtsi | 44 clks: clks@80000000 { label 95 clocks = <&clks CLPS711X_CLK_BUS>; 112 clocks = <&clks CLPS711X_CLK_BUS>; 120 clocks = <&clks CLPS711X_CLK_TIMER1>; 127 clocks = <&clks CLPS711X_CLK_TIMER2>; 134 clocks = <&clks CLPS711X_CLK_PWM>; 142 clocks = <&clks CLPS711X_CLK_UART>; 152 clocks = <&clks CLPS711X_CLK_SPI>; 166 clocks = <&clks CLPS711X_CLK_UART> [all...] |
imx1.dtsi | 51 clocks = <&clks IMX1_CLK_MCU>; 82 clocks = <&clks IMX1_CLK_HCLK>, 83 <&clks IMX1_CLK_PER1>; 91 clocks = <&clks IMX1_CLK_HCLK>, 92 <&clks IMX1_CLK_PER1>; 100 clocks = <&clks IMX1_CLK_DUMMY>, 101 <&clks IMX1_CLK_DUMMY>, 102 <&clks IMX1_CLK_PER2>; 111 clocks = <&clks IMX1_CLK_HCLK>, 112 <&clks IMX1_CLK_PER1> 199 clks: ccm@21b000 { label [all...] |
imx23.dtsi | 71 clocks = <&clks 15>; 87 clocks = <&clks 34>; 97 clocks = <&clks 33>; 430 clocks = <&clks 16>; 450 clocks = <&clks 15>; 462 clocks = <&clks 38>; 469 clocks = <&clks 33>; 488 clks: clkctrl@80040000 { label 532 clocks = <&clks 26>; 564 clocks = <&clks 30> [all...] |
imx31.dtsi | 77 clocks = <&clks 33>; 87 clocks = <&clks 35>; 97 clocks = <&clks 26>; 105 clocks = <&clks 10>, <&clks 30>; 114 clocks = <&clks 10>, <&clks 31>; 123 clocks = <&clks 34>; 133 clocks = <&clks 10>, <&clks 53> 235 clks: ccm@53f80000{ label [all...] |
imx35.dtsi | 81 clocks = <&clks 51>; 92 clocks = <&clks 53>; 101 clocks = <&clks 9>, <&clks 70>; 110 clocks = <&clks 9>, <&clks 71>; 121 clocks = <&clks 52>; 132 clocks = <&clks 68>; 145 clocks = <&clks 35 &clks 35> 209 clks: ccm@53f80000 { label in label:aips2 [all...] |
imx50.dtsi | 91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 123 <&clks IMX5_CLK_DUMMY>, 124 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 135 <&clks IMX5_CLK_DUMMY>, 136 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 147 <&clks IMX5_CLK_UART3_PER_GATE>; 158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE> 338 clks: ccm@53fd4000{ label [all...] |
imx23.dtsi | 71 clocks = <&clks 15>; 87 clocks = <&clks 34>; 97 clocks = <&clks 33>; 430 clocks = <&clks 16>; 450 clocks = <&clks 15>; 462 clocks = <&clks 38>; 469 clocks = <&clks 33>; 488 clks: clkctrl@80040000 { label 532 clocks = <&clks 26>; 564 clocks = <&clks 30> [all...] |
imx31.dtsi | 77 clocks = <&clks 33>; 87 clocks = <&clks 35>; 97 clocks = <&clks 26>; 105 clocks = <&clks 10>, <&clks 30>; 114 clocks = <&clks 10>, <&clks 31>; 123 clocks = <&clks 34>; 133 clocks = <&clks 10>, <&clks 53> 235 clks: ccm@53f80000{ label [all...] |
imx35.dtsi | 81 clocks = <&clks 51>; 92 clocks = <&clks 53>; 101 clocks = <&clks 9>, <&clks 70>; 110 clocks = <&clks 9>, <&clks 71>; 121 clocks = <&clks 52>; 132 clocks = <&clks 68>; 145 clocks = <&clks 35 &clks 35> 209 clks: ccm@53f80000 { label in label:aips2 [all...] |
imx50.dtsi | 91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 123 <&clks IMX5_CLK_DUMMY>, 124 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 135 <&clks IMX5_CLK_DUMMY>, 136 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 147 <&clks IMX5_CLK_UART3_PER_GATE>; 158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE> 338 clks: ccm@53fd4000{ label [all...] |
imx25.dtsi | 95 clocks = <&clks 48>; 106 clocks = <&clks 48>; 116 clocks = <&clks 75>, <&clks 75>; 125 clocks = <&clks 76>, <&clks 76>; 134 clocks = <&clks 120>, <&clks 57>; 143 clocks = <&clks 121>, <&clks 57> 347 clks: ccm@53f80000 { label [all...] |
imx27.dtsi | 72 clocks = <&clks IMX27_CLK_CPU_DIV>; 95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>, 96 <&clks IMX27_CLK_DMA_AHB_GATE>; 106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>; 113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, 114 <&clks IMX27_CLK_PER1_GATE>; 122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>, 123 <&clks IMX27_CLK_PER1_GATE>; 131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>, 132 <&clks IMX27_CLK_PER1_GATE> 537 clks: ccm@10027000{ label [all...] |
imx51.dtsi | 83 clocks = <&clks IMX5_CLK_CPU_PODF>; 102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>; 135 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; 145 clocks = <&clks IMX5_CLK_IPU_GATE>, 146 <&clks IMX5_CLK_IPU_DI0_GATE>, 147 <&clks IMX5_CLK_IPU_DI1_GATE>; 192 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 193 <&clks IMX5_CLK_DUMMY>, 194 <&clks IMX5_CLK_ESDHC1_PER_GATE> 449 clks: ccm@73fd4000{ label [all...] |
pxa3xx.dtsi | 135 clocks = <&clks CLK_PWRI2C>; 145 clocks = <&clks CLK_NAND>; 170 clocks = <&clks CLK_GPIO>; 184 clocks = <&clks CLK_MMC1>; 195 clocks = <&clks CLK_MMC2>; 206 clocks = <&clks CLK_MMC3>; 217 clocks = <&clks CLK_USBH>; 225 clocks = <&clks CLK_PWM0>; 233 clocks = <&clks CLK_PWM1>; 241 clocks = <&clks CLK_PWM0> 311 clks: clocks { label [all...] |
/src/sys/arch/arm/sunxi/ |
sunxi_de2_ccu.c | 82 struct sunxi_ccu_clk *clks; member in struct:sunxi_de2_ccu_config 89 .clks = sun8i_h3_de2_ccu_clks, 96 .clks = sun8i_h3_de2_ccu_clks, 139 sc->sc_clks = conf->clks;
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sunxi_de2_ccu.c | 82 struct sunxi_ccu_clk *clks; member in struct:sunxi_de2_ccu_config 89 .clks = sun8i_h3_de2_ccu_clks, 96 .clks = sun8i_h3_de2_ccu_clks, 139 sc->sc_clks = conf->clks;
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/src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
amdgpu_display_mode_vba.c | 379 display_clocks_and_cfg_st *clks = &pipes[j].clks_cfg; local in function:fetch_pipe_params 519 mode_lib->vba.DPPCLK[mode_lib->vba.NumberOfActivePlanes] = clks->dppclk_mhz;
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