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      1 // SPDX-License-Identifier: GPL-2.0+
      2 //
      3 // Copyright (C) 2014 Alexander Shiyan <shc_work (a] mail.ru>
      4 
      5 #include "imx1-pinfunc.h"
      6 
      7 #include <dt-bindings/clock/imx1-clock.h>
      8 #include <dt-bindings/gpio/gpio.h>
      9 #include <dt-bindings/interrupt-controller/irq.h>
     10 
     11 / {
     12 	#address-cells = <1>;
     13 	#size-cells = <1>;
     14 	/*
     15 	 * The decompressor and also some bootloaders rely on a
     16 	 * pre-existing /chosen node to be available to insert the
     17 	 * command line and merge other ATAGS info.
     18 	 */
     19 	chosen {};
     20 
     21 	aliases {
     22 		gpio0 = &gpio1;
     23 		gpio1 = &gpio2;
     24 		gpio2 = &gpio3;
     25 		gpio3 = &gpio4;
     26 		i2c0 = &i2c;
     27 		serial0 = &uart1;
     28 		serial1 = &uart2;
     29 		serial2 = &uart3;
     30 		spi0 = &cspi1;
     31 		spi1 = &cspi2;
     32 	};
     33 
     34 	aitc: aitc-interrupt-controller@223000 {
     35 		compatible = "fsl,imx1-aitc", "fsl,avic";
     36 		interrupt-controller;
     37 		#interrupt-cells = <1>;
     38 		reg = <0x00223000 0x1000>;
     39 	};
     40 
     41 	cpus {
     42 		#size-cells = <0>;
     43 		#address-cells = <1>;
     44 
     45 		cpu@0 {
     46 			device_type = "cpu";
     47 			reg = <0>;
     48 			compatible = "arm,arm920t";
     49 			operating-points = <200000 1900000>;
     50 			clock-latency = <62500>;
     51 			clocks = <&clks IMX1_CLK_MCU>;
     52 			voltage-tolerance = <5>;
     53 		};
     54 	};
     55 
     56 	clocks {
     57 		clk32 {
     58 			compatible = "fsl,imx-clk32", "fixed-clock";
     59 			#clock-cells = <0>;
     60 			clock-frequency = <32000>;
     61 		};
     62 	};
     63 
     64 	soc {
     65 		#address-cells = <1>;
     66 		#size-cells = <1>;
     67 		compatible = "simple-bus";
     68 		interrupt-parent = <&aitc>;
     69 		ranges;
     70 
     71 		aipi@200000 {
     72 			compatible = "fsl,aipi-bus", "simple-bus";
     73 			#address-cells = <1>;
     74 			#size-cells = <1>;
     75 			reg = <0x00200000 0x10000>;
     76 			ranges;
     77 
     78 			gpt1: timer@202000 {
     79 				compatible = "fsl,imx1-gpt";
     80 				reg = <0x00202000 0x1000>;
     81 				interrupts = <59>;
     82 				clocks = <&clks IMX1_CLK_HCLK>,
     83 					 <&clks IMX1_CLK_PER1>;
     84 				clock-names = "ipg", "per";
     85 			};
     86 
     87 			gpt2: timer@203000 {
     88 				compatible = "fsl,imx1-gpt";
     89 				reg = <0x00203000 0x1000>;
     90 				interrupts = <58>;
     91 				clocks = <&clks IMX1_CLK_HCLK>,
     92 					 <&clks IMX1_CLK_PER1>;
     93 				clock-names = "ipg", "per";
     94 			};
     95 
     96 			fb: fb@205000 {
     97 				compatible = "fsl,imx1-fb";
     98 				reg = <0x00205000 0x1000>;
     99 				interrupts = <14>;
    100 				clocks = <&clks IMX1_CLK_DUMMY>,
    101 					 <&clks IMX1_CLK_DUMMY>,
    102 					 <&clks IMX1_CLK_PER2>;
    103 				clock-names = "ipg", "ahb", "per";
    104 				status = "disabled";
    105 			};
    106 
    107 			uart1: serial@206000 {
    108 				compatible = "fsl,imx1-uart";
    109 				reg = <0x00206000 0x1000>;
    110 				interrupts = <30 29 26>;
    111 				clocks = <&clks IMX1_CLK_HCLK>,
    112 					 <&clks IMX1_CLK_PER1>;
    113 				clock-names = "ipg", "per";
    114 				status = "disabled";
    115 			};
    116 
    117 			uart2: serial@207000 {
    118 				compatible = "fsl,imx1-uart";
    119 				reg = <0x00207000 0x1000>;
    120 				interrupts = <24 23 20>;
    121 				clocks = <&clks IMX1_CLK_HCLK>,
    122 					 <&clks IMX1_CLK_PER1>;
    123 				clock-names = "ipg", "per";
    124 				status = "disabled";
    125 			};
    126 
    127 			pwm: pwm@208000 {
    128 				#pwm-cells = <3>;
    129 				compatible = "fsl,imx1-pwm";
    130 				reg = <0x00208000 0x1000>;
    131 				interrupts = <34>;
    132 				clocks = <&clks IMX1_CLK_DUMMY>,
    133 					 <&clks IMX1_CLK_PER1>;
    134 				clock-names = "ipg", "per";
    135 			};
    136 
    137 			dma: dma@209000 {
    138 				compatible = "fsl,imx1-dma";
    139 				reg = <0x00209000 0x1000>;
    140 				interrupts = <61 60>;
    141 				clocks = <&clks IMX1_CLK_HCLK>,
    142 					 <&clks IMX1_CLK_DMA_GATE>;
    143 				clock-names = "ipg", "ahb";
    144 				#dma-cells = <1>;
    145 			};
    146 
    147 			uart3: serial@20a000 {
    148 				compatible = "fsl,imx1-uart";
    149 				reg = <0x0020a000 0x1000>;
    150 				interrupts = <54 4 1>;
    151 				clocks = <&clks IMX1_CLK_UART3_GATE>,
    152 					 <&clks IMX1_CLK_PER1>;
    153 				clock-names = "ipg", "per";
    154 				status = "disabled";
    155 			};
    156 		};
    157 
    158 		aipi@210000 {
    159 			compatible = "fsl,aipi-bus", "simple-bus";
    160 			#address-cells = <1>;
    161 			#size-cells = <1>;
    162 			reg = <0x00210000 0x10000>;
    163 			ranges;
    164 
    165 			cspi1: spi@213000 {
    166 				#address-cells = <1>;
    167 				#size-cells = <0>;
    168 				compatible = "fsl,imx1-cspi";
    169 				reg = <0x00213000 0x1000>;
    170 				interrupts = <41>;
    171 				clocks = <&clks IMX1_CLK_DUMMY>,
    172 					 <&clks IMX1_CLK_PER1>;
    173 				clock-names = "ipg", "per";
    174 				status = "disabled";
    175 			};
    176 
    177 			i2c: i2c@217000 {
    178 				#address-cells = <1>;
    179 				#size-cells = <0>;
    180 				compatible = "fsl,imx1-i2c";
    181 				reg = <0x00217000 0x1000>;
    182 				interrupts = <39>;
    183 				clocks = <&clks IMX1_CLK_HCLK>;
    184 				status = "disabled";
    185 			};
    186 
    187 			cspi2: spi@219000 {
    188 				#address-cells = <1>;
    189 				#size-cells = <0>;
    190 				compatible = "fsl,imx1-cspi";
    191 				reg = <0x00219000 0x1000>;
    192 				interrupts = <40>;
    193 				clocks = <&clks IMX1_CLK_DUMMY>,
    194 					 <&clks IMX1_CLK_PER1>;
    195 				clock-names = "ipg", "per";
    196 				status = "disabled";
    197 			};
    198 
    199 			clks: ccm@21b000 {
    200 				compatible = "fsl,imx1-ccm";
    201 				reg = <0x0021b000 0x1000>;
    202 				#clock-cells = <1>;
    203 			};
    204 
    205 			iomuxc: iomuxc@21c000 {
    206 				compatible = "fsl,imx1-iomuxc";
    207 				reg = <0x0021c000 0x1000>;
    208 				#address-cells = <1>;
    209 				#size-cells = <1>;
    210 				ranges;
    211 
    212 				gpio1: gpio@21c000 {
    213 					compatible = "fsl,imx1-gpio";
    214 					reg = <0x0021c000 0x100>;
    215 					interrupts = <11>;
    216 					gpio-controller;
    217 					#gpio-cells = <2>;
    218 					interrupt-controller;
    219 					#interrupt-cells = <2>;
    220 				};
    221 
    222 				gpio2: gpio@21c100 {
    223 					compatible = "fsl,imx1-gpio";
    224 					reg = <0x0021c100 0x100>;
    225 					interrupts = <12>;
    226 					gpio-controller;
    227 					#gpio-cells = <2>;
    228 					interrupt-controller;
    229 					#interrupt-cells = <2>;
    230 				};
    231 
    232 				gpio3: gpio@21c200 {
    233 					compatible = "fsl,imx1-gpio";
    234 					reg = <0x0021c200 0x100>;
    235 					interrupts = <13>;
    236 					gpio-controller;
    237 					#gpio-cells = <2>;
    238 					interrupt-controller;
    239 					#interrupt-cells = <2>;
    240 				};
    241 
    242 				gpio4: gpio@21c300 {
    243 					compatible = "fsl,imx1-gpio";
    244 					reg = <0x0021c300 0x100>;
    245 					interrupts = <62>;
    246 					gpio-controller;
    247 					#gpio-cells = <2>;
    248 					interrupt-controller;
    249 					#interrupt-cells = <2>;
    250 				};
    251 			};
    252 		};
    253 
    254 		weim: weim@220000 {
    255 			#address-cells = <2>;
    256 			#size-cells = <1>;
    257 			compatible = "fsl,imx1-weim";
    258 			reg = <0x00220000 0x1000>;
    259 			clocks = <&clks IMX1_CLK_DUMMY>;
    260 			ranges = <
    261 				0 0 0x10000000 0x02000000
    262 				1 0 0x12000000 0x01000000
    263 				2 0 0x13000000 0x01000000
    264 				3 0 0x14000000 0x01000000
    265 				4 0 0x15000000 0x01000000
    266 				5 0 0x16000000 0x01000000
    267 			>;
    268 			status = "disabled";
    269 		};
    270 
    271 		esram: esram@300000 {
    272 			compatible = "mmio-sram";
    273 			reg = <0x00300000 0x20000>;
    274 		};
    275 	};
    276 };
    277