| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 3237 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v10_0_crtc_irq
3242 if (disp_int & interrupt_status_offsets[crtc].vblank)
3254 if (disp_int & interrupt_status_offsets[crtc].vline)
3274 uint32_t disp_int, mask; local in function:dce_v10_0_hpd_irq
3283 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3286 if (disp_int & mask) {
|
| amdgpu_dce_v11_0.c | 3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v11_0_crtc_irq
3369 if (disp_int & interrupt_status_offsets[crtc].vblank)
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3401 uint32_t disp_int, mask; local in function:dce_v11_0_hpd_irq
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3413 if (disp_int & mask) {
|
| amdgpu_dce_v6_0.c | 2958 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v6_0_crtc_irq
2964 if (disp_int & interrupt_status_offsets[crtc].vblank)
2975 if (disp_int & interrupt_status_offsets[crtc].vline)
3070 uint32_t disp_int, mask, tmp; local in function:dce_v6_0_hpd_irq
3079 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3082 if (disp_int & mask) {
|
| amdgpu_dce_v8_0.c | 3048 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v8_0_crtc_irq
3054 if (disp_int & interrupt_status_offsets[crtc].vblank)
3065 if (disp_int & interrupt_status_offsets[crtc].vline)
3160 uint32_t disp_int, mask, tmp; local in function:dce_v8_0_hpd_irq
3169 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3172 if (disp_int & mask) {
|
| amdgpu_dce_v10_0.c | 3237 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v10_0_crtc_irq
3242 if (disp_int & interrupt_status_offsets[crtc].vblank)
3254 if (disp_int & interrupt_status_offsets[crtc].vline)
3274 uint32_t disp_int, mask; local in function:dce_v10_0_hpd_irq
3283 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3286 if (disp_int & mask) {
|
| amdgpu_dce_v11_0.c | 3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v11_0_crtc_irq
3369 if (disp_int & interrupt_status_offsets[crtc].vblank)
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3401 uint32_t disp_int, mask; local in function:dce_v11_0_hpd_irq
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3413 if (disp_int & mask) {
|
| amdgpu_dce_v6_0.c | 2958 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v6_0_crtc_irq
2964 if (disp_int & interrupt_status_offsets[crtc].vblank)
2975 if (disp_int & interrupt_status_offsets[crtc].vline)
3070 uint32_t disp_int, mask, tmp; local in function:dce_v6_0_hpd_irq
3079 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3082 if (disp_int & mask) {
|
| amdgpu_dce_v8_0.c | 3048 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg); local in function:dce_v8_0_crtc_irq
3054 if (disp_int & interrupt_status_offsets[crtc].vblank)
3065 if (disp_int & interrupt_status_offsets[crtc].vline)
3160 uint32_t disp_int, mask, tmp; local in function:dce_v8_0_hpd_irq
3169 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3172 if (disp_int & mask) {
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 4621 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:evergreen_irq_ack
4625 disp_int[i] = RREG32(evergreen_disp_int_status[i]);
4640 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
4643 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
4650 if (disp_int[i] & DC_HPD1_INTERRUPT)
4655 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
4708 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:evergreen_irq_process
4787 if (!(disp_int[crtc_idx] & mask))
[all...] |
| radeon_evergreen.c | 4621 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:evergreen_irq_ack
4625 disp_int[i] = RREG32(evergreen_disp_int_status[i]);
4640 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
4643 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
4650 if (disp_int[i] & DC_HPD1_INTERRUPT)
4655 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
4708 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:evergreen_irq_process
4787 if (!(disp_int[crtc_idx] & mask))
[all...] |
| radeon_si.c | 6155 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:si_irq_ack
6162 disp_int[i] = RREG32(si_disp_int_status[i]);
6176 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
6179 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
6186 if (disp_int[i] & DC_HPD1_INTERRUPT)
6191 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
6254 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:si_irq_process
6332 if (!(disp_int[crtc_idx] & mask))
[all...] |
| radeon_si.c | 6155 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:si_irq_ack
6162 disp_int[i] = RREG32(si_disp_int_status[i]);
6176 if (disp_int[j] & LB_D1_VBLANK_INTERRUPT)
6179 if (disp_int[j] & LB_D1_VLINE_INTERRUPT)
6186 if (disp_int[i] & DC_HPD1_INTERRUPT)
6191 if (disp_int[i] & DC_HPD1_RX_INTERRUPT)
6254 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; local in function:si_irq_process
6332 if (!(disp_int[crtc_idx] & mask))
[all...] |
| radeon.h | 791 u32 disp_int; member in struct:r500_irq_stat_regs
796 u32 disp_int; member in struct:r600_irq_stat_regs
806 u32 disp_int[6]; member in struct:evergreen_irq_stat_regs
812 u32 disp_int; member in struct:cik_irq_stat_regs
|
| radeon.h | 791 u32 disp_int; member in struct:r500_irq_stat_regs
796 u32 disp_int; member in struct:r600_irq_stat_regs
806 u32 disp_int[6]; member in struct:evergreen_irq_stat_regs
812 u32 disp_int; member in struct:cik_irq_stat_regs
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