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Searched defs:f32_cntl (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c	`354 u32 f32_cntl, phase_quantum = 0; local in function:cik_ctx_switch_enable 382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);`
amdgpu_sdma_v2_4.c	`390 u32 f32_cntl; local in function:sdma_v2_4_enable 399 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 401 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 403 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 404 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);`
amdgpu_cik_sdma.c	`354 u32 f32_cntl, phase_quantum = 0; local in function:cik_ctx_switch_enable 382 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 384 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 393 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 397 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);`
amdgpu_sdma_v2_4.c	`390 u32 f32_cntl; local in function:sdma_v2_4_enable 399 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]); 401 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); 403 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); 404 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);`
amdgpu_sdma_v3_0.c	`564 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v3_0_ctx_switch_enable 592 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 607 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL 625 u32 f32_cntl; local in function:sdma_v3_0_enable [all...]`
amdgpu_sdma_v4_0.c	`996 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v4_0_ctx_switch_enable 1024 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1025 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1032 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1047 u32 f32_cntl; local in function:sdma_v4_0_enable 1058 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1059 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1060 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); [all...]`
amdgpu_sdma_v5_0.c	539 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v5_0_ctx_switch_enable 567 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 578 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 593 u32 f32_cntl; local in function:sdma_v5_0_enable 602 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 604 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); [all...]
amdgpu_sdma_v3_0.c	`564 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v3_0_ctx_switch_enable 592 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]); 594 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 596 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 605 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 607 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL 625 u32 f32_cntl; local in function:sdma_v3_0_enable [all...]`
amdgpu_sdma_v4_0.c	`996 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v4_0_ctx_switch_enable 1024 f32_cntl = RREG32_SDMA(i, mmSDMA0_CNTL); 1025 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 1032 WREG32_SDMA(i, mmSDMA0_CNTL, f32_cntl); 1047 u32 f32_cntl; local in function:sdma_v4_0_enable 1058 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL); 1059 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 1060 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl); [all...]`
amdgpu_sdma_v5_0.c	539 u32 f32_cntl, phase_quantum = 0; local in function:sdma_v5_0_ctx_switch_enable 567 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); 568 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL, 578 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl); 593 u32 f32_cntl; local in function:sdma_v5_0_enable 602 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); 603 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1); 604 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); [all...]

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