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    Searched defs:gate (Results 1 - 25 of 60) sorted by relevancy

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  /src/sys/arch/arm/nxp/
imx_ccm_gate.c 43 struct imx_ccm_gate *gate = &clk->u.gate; local in function:imx_ccm_gate_enable
48 val = CCM_READ(sc, clk->regidx, gate->reg);
50 val |= gate->mask;
52 val &= ~gate->mask;
53 CCM_WRITE(sc, clk->regidx, gate->reg, val);
62 struct imx_ccm_gate *gate = &clk->u.gate; local in function:imx_ccm_gate_get_parent
66 return gate->parent;
imx_ccm_gate.c 43 struct imx_ccm_gate *gate = &clk->u.gate; local in function:imx_ccm_gate_enable
48 val = CCM_READ(sc, clk->regidx, gate->reg);
50 val |= gate->mask;
52 val &= ~gate->mask;
53 CCM_WRITE(sc, clk->regidx, gate->reg, val);
62 struct imx_ccm_gate *gate = &clk->u.gate; local in function:imx_ccm_gate_get_parent
66 return gate->parent;
imx6_ccm.c 566 struct imx6_clk_gate *gate = &iclk->clk.gate; local in function:imxccm_clk_enable_gate
571 if (gate->base == IMX6_CLK_REG_CCM_ANALOG)
576 uint32_t v = bus_space_read_4(sc->sc_iot, ioh, gate->reg);
578 if (gate->exclusive_mask)
579 v &= ~gate->exclusive_mask;
580 v |= gate->mask;
582 if (gate->exclusive_mask)
583 v |= gate->exclusive_mask;
584 v &= ~gate->mask
    [all...]
  /src/sys/arch/arm/sunxi/
sunxi_ccu_gate.c 43 struct sunxi_ccu_gate *gate = &clk->u.gate; local in function:sunxi_ccu_gate_enable
48 val = CCU_READ(sc, gate->reg);
50 val |= gate->mask;
52 val &= ~gate->mask;
53 CCU_WRITE(sc, gate->reg, val);
61 struct sunxi_ccu_gate *gate = &clk->u.gate; local in function:sunxi_ccu_gate_get_parent
65 return gate->parent;
sunxi_ccu_gate.c 43 struct sunxi_ccu_gate *gate = &clk->u.gate; local in function:sunxi_ccu_gate_enable
48 val = CCU_READ(sc, gate->reg);
50 val |= gate->mask;
52 val &= ~gate->mask;
53 CCU_WRITE(sc, gate->reg, val);
61 struct sunxi_ccu_gate *gate = &clk->u.gate; local in function:sunxi_ccu_gate_get_parent
65 return gate->parent;
sunxi_gates.c 78 struct sunxi_gate *gate; local in function:sunxi_gates_clock_decode
85 TAILQ_FOREACH(gate, &sc->sc_gates, gates)
86 if (gate->index == index)
87 return &gate->base;
100 struct sunxi_gate *gate; local in function:sunxi_gates_clock_get
102 TAILQ_FOREACH(gate, &sc->sc_gates, gates)
103 if (strcmp(gate->base.name, name) == 0)
104 return &gate->base;
118 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_get_rate
125 const bus_size_t gate_reg = GATE_REG(gate->index)
138 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_enable
155 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_disable
188 struct sunxi_gate *gate; local in function:sunxi_gates_print
219 struct sunxi_gate *gate; local in function:sunxi_gates_attach
    [all...]
sunxi_gates.c 78 struct sunxi_gate *gate; local in function:sunxi_gates_clock_decode
85 TAILQ_FOREACH(gate, &sc->sc_gates, gates)
86 if (gate->index == index)
87 return &gate->base;
100 struct sunxi_gate *gate; local in function:sunxi_gates_clock_get
102 TAILQ_FOREACH(gate, &sc->sc_gates, gates)
103 if (strcmp(gate->base.name, name) == 0)
104 return &gate->base;
118 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_get_rate
125 const bus_size_t gate_reg = GATE_REG(gate->index)
138 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_enable
155 struct sunxi_gate *gate = (struct sunxi_gate *)clkp; local in function:sunxi_gates_clock_disable
188 struct sunxi_gate *gate; local in function:sunxi_gates_print
219 struct sunxi_gate *gate; local in function:sunxi_gates_attach
    [all...]
  /src/sys/arch/arm/amlogic/
meson_clk_gate.c 43 struct meson_clk_gate *gate = &clk->u.gate; local in function:meson_clk_gate_enable
49 set = (gate->flags & MESON_CLK_GATE_SET_TO_DISABLE) ? !enable : enable;
53 val = CLK_READ(sc, gate->reg);
55 val |= gate->mask;
57 val &= ~gate->mask;
58 CLK_WRITE(sc, gate->reg, val);
68 struct meson_clk_gate *gate = &clk->u.gate; local in function:meson_clk_gate_get_parent
72 return gate->parent
    [all...]
meson_clk_gate.c 43 struct meson_clk_gate *gate = &clk->u.gate; local in function:meson_clk_gate_enable
49 set = (gate->flags & MESON_CLK_GATE_SET_TO_DISABLE) ? !enable : enable;
53 val = CLK_READ(sc, gate->reg);
55 val |= gate->mask;
57 val &= ~gate->mask;
58 CLK_WRITE(sc, gate->reg, val);
68 struct meson_clk_gate *gate = &clk->u.gate; local in function:meson_clk_gate_get_parent
72 return gate->parent
    [all...]
  /src/sys/arch/arm/rockchip/
rk_cru_gate.c 43 struct rk_cru_gate *gate = &clk->u.gate; local in function:rk_cru_gate_enable
47 const uint32_t write_mask = gate->mask << 16;
48 const uint32_t write_val = enable ? 0 : gate->mask;
50 CRU_WRITE(sc, gate->reg, write_mask | write_val);
59 struct rk_cru_gate *gate = &clk->u.gate; local in function:rk_cru_gate_get_parent
63 return gate->parent;
rk_cru_gate.c 43 struct rk_cru_gate *gate = &clk->u.gate; local in function:rk_cru_gate_enable
47 const uint32_t write_mask = gate->mask << 16;
48 const uint32_t write_val = enable ? 0 : gate->mask;
50 CRU_WRITE(sc, gate->reg, write_mask | write_val);
59 struct rk_cru_gate *gate = &clk->u.gate; local in function:rk_cru_gate_get_parent
63 return gate->parent;
  /src/sys/netatalk/
ddp_output.c 120 struct sockaddr_at gate; local in function:ddp_route
192 gate = *satocsat(rtcache_getdst(ro));
194 gate = *satosat(rt->rt_gateway);
212 error = if_output_lock(ifp, ifp, m, (struct sockaddr *)&gate, NULL);
ddp_output.c 120 struct sockaddr_at gate; local in function:ddp_route
192 gate = *satocsat(rtcache_getdst(ro));
194 gate = *satosat(rt->rt_gateway);
212 error = if_output_lock(ifp, ifp, m, (struct sockaddr *)&gate, NULL);
at_control.c 796 struct sockaddr_at addr, mask, *gate; local in function:aa_dosingleroute
810 gate = satosat(ifa->ifa_dstaddr);
813 gate = satosat(ifa->ifa_addr);
818 ntohs(gate->sat_addr.s_net), gate->sat_addr.s_node);
821 (struct sockaddr *) gate, (struct sockaddr *) &mask, flags, NULL));
at_control.c 796 struct sockaddr_at addr, mask, *gate; local in function:aa_dosingleroute
810 gate = satosat(ifa->ifa_dstaddr);
813 gate = satosat(ifa->ifa_addr);
818 ntohs(gate->sat_addr.s_net), gate->sat_addr.s_node);
821 (struct sockaddr *) gate, (struct sockaddr *) &mask, flags, NULL));
  /src/usr.bin/rump_dhcpclient/
net.h 84 struct in_addr gate; member in struct:rt
126 #define add_route(iface, dest, mask, gate, metric) \
127 if_route(iface, dest, mask, gate, metric, 1)
128 #define change_route(iface, dest, mask, gate, metric) \
129 if_route(iface, dest, mask, gate, metric, 0)
130 #define del_route(iface, dest, mask, gate, metric) \
131 if_route(iface, dest, mask, gate, metric, -1)
132 #define del_src_route(iface, dest, mask, gate, metric) \
133 if_route(iface, dest, mask, gate, metric, -2)
net.h 84 struct in_addr gate; member in struct:rt
126 #define add_route(iface, dest, mask, gate, metric) \
127 if_route(iface, dest, mask, gate, metric, 1)
128 #define change_route(iface, dest, mask, gate, metric) \
129 if_route(iface, dest, mask, gate, metric, 0)
130 #define del_route(iface, dest, mask, gate, metric) \
131 if_route(iface, dest, mask, gate, metric, -1)
132 #define del_src_route(iface, dest, mask, gate, metric) \
133 if_route(iface, dest, mask, gate, metric, -2)
  /src/sys/arch/arm/samsung/
exynos_clock.h 79 struct exynos_gate_clk gate; member in union:exynos_clk::__anoncaafd60b010a
exynos_clock.h 79 struct exynos_gate_clk gate; member in union:exynos_clk::__anoncaafd60b010a
  /src/sbin/routed/
input.c 153 naddr gate, mask, v1_mask, dst, ddst_h = 0; local in function:input
640 gate = FROM_NADDR;
649 gate = n->n_nhop;
753 new.rts_gate = gate;
input.c 153 naddr gate, mask, v1_mask, dst, ddst_h = 0; local in function:input
640 gate = FROM_NADDR;
649 gate = n->n_nhop;
753 new.rts_gate = gate;
  /src/sys/arch/arm/nvidia/
tegra_clock.h 86 struct tegra_gate_clk gate; member in union:tegra_clk::__anon56bd0515010a
tegra_clock.h 86 struct tegra_gate_clk gate; member in union:tegra_clk::__anon56bd0515010a
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vce_v2_0.c 558 bool gate = false; local in function:vce_v2_0_set_clockgating_state
564 gate = true;
568 vce_v2_0_enable_mgcg(adev, gate, sw_cg);
amdgpu_vce_v2_0.c 558 bool gate = false; local in function:vce_v2_0_set_clockgating_state
564 gate = true;
568 vce_v2_0_enable_mgcg(adev, gate, sw_cg);

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