| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_rv730_dpm.c | 327 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); local
347 cpu_to_be32(initial_state->low.mclk);
361 cpu_to_be32(initial_state->low.sclk);
366 rv770_get_seq_value(rdev, &initial_state->low);
369 initial_state->low.vddc,
384 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
|
| radeon_rv730_dpm.c | 327 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); local
347 cpu_to_be32(initial_state->low.mclk);
361 cpu_to_be32(initial_state->low.sclk);
366 rv770_get_seq_value(rdev, &initial_state->low);
369 initial_state->low.vddc,
384 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
|
| radeon_cypress_dpm.c | 1244 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); local
1268 cpu_to_be32(initial_state->low.mclk);
1282 cpu_to_be32(initial_state->low.sclk);
1290 initial_state->low.vddc,
1296 initial_state->low.vddci,
1312 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1320 initial_state->low.mclk);
1322 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
|
| radeon_cypress_dpm.c | 1244 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state); local
1268 cpu_to_be32(initial_state->low.mclk);
1282 cpu_to_be32(initial_state->low.sclk);
1290 initial_state->low.vddc,
1296 initial_state->low.vddci,
1312 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1320 initial_state->low.mclk);
1322 if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
|
| radeon_rv770_dpm.c | 1031 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); local
1054 cpu_to_be32(initial_state->low.mclk);
1068 cpu_to_be32(initial_state->low.sclk);
1073 rv770_get_seq_value(rdev, &initial_state->low);
1076 initial_state->low.vddc,
1090 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1097 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)
1099 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10;
1103 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
|
| radeon_rv770_dpm.c | 1031 struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); local
1054 cpu_to_be32(initial_state->low.mclk);
1068 cpu_to_be32(initial_state->low.sclk);
1073 rv770_get_seq_value(rdev, &initial_state->low);
1076 initial_state->low.vddc,
1090 if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
1097 if (initial_state->low.mclk <= pi->mclk_strobe_mode_threshold)
1099 rv740_get_mclk_frequency_ratio(initial_state->low.mclk) | 0x10;
1103 if (initial_state->low.mclk >= pi->mclk_edc_enable_threshold)
|
| radeon_ni_dpm.c | 1689 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); local
1713 cpu_to_be32(initial_state->performance_levels[0].mclk);
1728 cpu_to_be32(initial_state->performance_levels[0].sclk);
1735 initial_state->performance_levels[0].vddc,
1752 initial_state->performance_levels[0].vddci,
1770 initial_state->performance_levels[0].mclk);
1772 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
|
| radeon_ni_dpm.c | 1689 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); local
1713 cpu_to_be32(initial_state->performance_levels[0].mclk);
1728 cpu_to_be32(initial_state->performance_levels[0].sclk);
1735 initial_state->performance_levels[0].vddc,
1752 initial_state->performance_levels[0].vddci,
1770 initial_state->performance_levels[0].mclk);
1772 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
|
| radeon_si_dpm.c | 4373 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); local
4400 cpu_to_be32(initial_state->performance_levels[0].mclk);
4416 cpu_to_be32(initial_state->performance_levels[0].sclk);
4424 initial_state->performance_levels[0].vddc,
4442 initial_state->performance_levels[0].vddci,
4448 initial_state->performance_levels[0].vddc,
4449 initial_state->performance_levels[0].sclk,
4450 initial_state->performance_levels[0].mclk,
4465 initial_state->performance_levels[0].mclk);
4467 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold
[all...] |
| radeon_si_dpm.c | 4373 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); local
4400 cpu_to_be32(initial_state->performance_levels[0].mclk);
4416 cpu_to_be32(initial_state->performance_levels[0].sclk);
4424 initial_state->performance_levels[0].vddc,
4442 initial_state->performance_levels[0].vddci,
4448 initial_state->performance_levels[0].vddc,
4449 initial_state->performance_levels[0].sclk,
4450 initial_state->performance_levels[0].mclk,
4465 initial_state->performance_levels[0].mclk);
4467 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold
[all...] |
| /src/external/bsd/ntp/dist/ntpd/ |
| keyword-gen.c | 359 u_short initial_state; local
395 initial_state = create_keyword_scanner();
403 printf("#define SCANNER_INIT_S %d\n\n", initial_state);
481 } while (this_state != initial_state);
494 i, (initial_state == i)
|
| keyword-gen.c | 359 u_short initial_state; local
395 initial_state = create_keyword_scanner();
403 printf("#define SCANNER_INIT_S %d\n\n", initial_state);
481 } while (this_state != initial_state);
494 i, (initial_state == i)
|
| /src/external/apache2/mDNSResponder/dist/ServiceRegistration/ |
| srp-dns-proxy.c | 638 update_state_t initial_state; local
642 initial_state = update->state;
864 if (update->state != initial_state) {
865 INFO("Update state changed from " PUB_S_SRP " to " PUB_S_SRP, update_state_name(initial_state),
|
| srp-dns-proxy.c | 638 update_state_t initial_state; local
642 initial_state = update->state;
864 if (update->state != initial_state) {
865 INFO("Update state changed from " PUB_S_SRP " to " PUB_S_SRP, update_state_name(initial_state),
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_si_dpm.c | 4839 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); local
4866 cpu_to_be32(initial_state->performance_levels[0].mclk);
4882 cpu_to_be32(initial_state->performance_levels[0].sclk);
4890 initial_state->performance_levels[0].vddc,
4908 initial_state->performance_levels[0].vddci,
4914 initial_state->performance_levels[0].vddc,
4915 initial_state->performance_levels[0].sclk,
4916 initial_state->performance_levels[0].mclk,
4929 initial_state->performance_levels[0].mclk);
4931 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold
[all...] |
| amdgpu_si_dpm.c | 4839 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state); local
4866 cpu_to_be32(initial_state->performance_levels[0].mclk);
4882 cpu_to_be32(initial_state->performance_levels[0].sclk);
4890 initial_state->performance_levels[0].vddc,
4908 initial_state->performance_levels[0].vddci,
4914 initial_state->performance_levels[0].vddc,
4915 initial_state->performance_levels[0].sclk,
4916 initial_state->performance_levels[0].mclk,
4929 initial_state->performance_levels[0].mclk);
4931 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold
[all...] |
