| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 2979 u32 lb_interrupt_mask; local in function:dce_v10_0_set_crtc_vblank_interrupt_state
2988 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2989 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2991 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2994 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2995 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3008 u32 lb_interrupt_mask; local in function:dce_v10_0_set_crtc_vline_interrupt_state
[all...] |
| amdgpu_dce_v11_0.c | 3105 u32 lb_interrupt_mask; local in function:dce_v11_0_set_crtc_vblank_interrupt_state
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3134 u32 lb_interrupt_mask; local in function:dce_v11_0_set_crtc_vline_interrupt_state
[all...] |
| amdgpu_dce_v8_0.c | 2867 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vblank_interrupt_state
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2901 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2905 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2906 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2907 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2918 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vline_interrupt_state
2951 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2952 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
[all...] |
| amdgpu_dce_v10_0.c | 2979 u32 lb_interrupt_mask; local in function:dce_v10_0_set_crtc_vblank_interrupt_state
2988 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2989 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
2991 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
2994 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
2995 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3008 u32 lb_interrupt_mask; local in function:dce_v10_0_set_crtc_vline_interrupt_state
[all...] |
| amdgpu_dce_v11_0.c | 3105 u32 lb_interrupt_mask; local in function:dce_v11_0_set_crtc_vblank_interrupt_state
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3134 u32 lb_interrupt_mask; local in function:dce_v11_0_set_crtc_vline_interrupt_state
[all...] |
| amdgpu_dce_v8_0.c | 2867 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vblank_interrupt_state
2900 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2901 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2902 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2905 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2906 lb_interrupt_mask |= LB_INTERRUPT_MASK__VBLANK_INTERRUPT_MASK_MASK;
2907 WREG32(mmLB_INTERRUPT_MASK + reg_block, lb_interrupt_mask);
2918 u32 reg_block, lb_interrupt_mask; local in function:dce_v8_0_set_crtc_vline_interrupt_state
2951 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + reg_block);
2952 lb_interrupt_mask &= ~LB_INTERRUPT_MASK__VLINE_INTERRUPT_MASK_MASK
[all...] |
