| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/ |
| amdgpu_irq_service_dce110.c | 217 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; local in function:dce110_vblank_set
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
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| amdgpu_irq_service_dce110.c | 217 uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; local in function:dce110_vblank_set
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg;
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/ |
| kfd_device_queue_manager.c | 80 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec local in function:is_pipe_enabled
85 if (test_bit(pipe_offset + i,
912 int pipe_offset = pipe * get_queues_per_pipe(dqm); local in function:initialize_nocpsch
915 if (test_bit(pipe_offset + queue,
1983 int pipe_offset = pipe * get_queues_per_pipe(dqm); local in function:dqm_debugfs_hqds
1986 if (!test_bit(pipe_offset + queue,
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| kfd_device_queue_manager.c | 80 int pipe_offset = mec * dqm->dev->shared_resources.num_pipe_per_mec local in function:is_pipe_enabled
85 if (test_bit(pipe_offset + i,
912 int pipe_offset = pipe * get_queues_per_pipe(dqm); local in function:initialize_nocpsch
915 if (test_bit(pipe_offset + queue,
1983 int pipe_offset = pipe * get_queues_per_pipe(dqm); local in function:dqm_debugfs_hqds
1986 if (!test_bit(pipe_offset + queue,
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| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_dce_v10_0.c | 604 u32 pipe_offset = amdgpu_crtc->crtc_id; local in function:dce_v10_0_line_buffer_adjust
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
639 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
642 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
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| amdgpu_dce_v11_0.c | 630 u32 pipe_offset = amdgpu_crtc->crtc_id; local in function:dce_v11_0_line_buffer_adjust
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
665 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
668 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
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| amdgpu_dce_v6_0.c | 1000 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local in function:dce_v6_0_line_buffer_adjust
1030 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1033 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| amdgpu_dce_v8_0.c | 541 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local in function:dce_v8_0_line_buffer_adjust
574 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
577 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| amdgpu_dce_v10_0.c | 604 u32 pipe_offset = amdgpu_crtc->crtc_id; local in function:dce_v10_0_line_buffer_adjust
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
639 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
642 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
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| amdgpu_dce_v11_0.c | 630 u32 pipe_offset = amdgpu_crtc->crtc_id; local in function:dce_v11_0_line_buffer_adjust
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
665 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
668 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
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| amdgpu_dce_v6_0.c | 1000 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local in function:dce_v6_0_line_buffer_adjust
1030 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1033 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| amdgpu_dce_v8_0.c | 541 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8; local in function:dce_v8_0_line_buffer_adjust
574 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
577 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| radeon_evergreen.c | 1834 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:evergreen_line_buffer_adjust
1875 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1878 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
2170 u32 pipe_offset = radeon_crtc->crtc_id * 16; local in function:evergreen_program_watermarks
2289 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2293 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2294 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2298 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2301 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2302 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
[all...] |
| radeon_evergreen.c | 1834 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:evergreen_line_buffer_adjust
1875 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1878 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
2170 u32 pipe_offset = radeon_crtc->crtc_id * 16; local in function:evergreen_program_watermarks
2289 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2293 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2294 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
2298 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
2301 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
2302 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
[all...] |
| radeon_si.c | 1984 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:dce6_line_buffer_adjust
2014 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
2017 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| radeon_si.c | 1984 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:dce6_line_buffer_adjust
2014 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
2017 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| radeon_cik.c | 8888 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:dce8_line_buffer_adjust
8920 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8923 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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| radeon_cik.c | 8888 u32 pipe_offset = radeon_crtc->crtc_id * 0x20; local in function:dce8_line_buffer_adjust
8920 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
8923 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
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