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    Searched defs:reg_data (Results 1 - 25 of 42) sorted by relevancy

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  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_compressor.c 253 uint32_t reg_data; local in function:dce110_compressor_disable_fbc
255 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
256 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
257 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
amdgpu_dce110_compressor.c 253 uint32_t reg_data; local in function:dce110_compressor_disable_fbc
255 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
256 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
257 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
amdgpu_dce110_compressor.c 253 uint32_t reg_data; local in function:dce110_compressor_disable_fbc
255 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
256 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
257 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
amdgpu_dce110_transform_v.c 641 uint32_t reg_data = 0; local in function:dce110_xfmv_set_pixel_storage_depth
666 reg_data,
672 reg_data,
677 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
amdgpu_dce110_transform_v.c 641 uint32_t reg_data = 0; local in function:dce110_xfmv_set_pixel_storage_depth
666 reg_data,
672 reg_data,
677 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
amdgpu_dce110_transform_v.c 641 uint32_t reg_data = 0; local in function:dce110_xfmv_set_pixel_storage_depth
666 reg_data,
672 reg_data,
677 dm_write_reg(xfm->ctx, mmLBV_DATA_FORMAT, reg_data);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce112/
amdgpu_dce112_compressor.c 428 uint32_t reg_data; local in function:dce112_compressor_disable_fbc
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
431 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
amdgpu_dce112_compressor.c 428 uint32_t reg_data; local in function:dce112_compressor_disable_fbc
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
431 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
amdgpu_dce112_compressor.c 428 uint32_t reg_data; local in function:dce112_compressor_disable_fbc
430 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL);
431 set_reg_field_value(reg_data, 0, FBC_CNTL, FBC_GRPH_COMP_EN);
432 dm_write_reg(compressor->ctx, mmFBC_CNTL, reg_data);
  /src/sys/external/bsd/drm2/dist/drm/amd/display/modules/stats/
stats.c 120 unsigned int reg_data; local in function:mod_stats_create
136 &reg_data, sizeof(unsigned int), &flag))
137 core_stats->enabled = reg_data;
143 &reg_data, sizeof(unsigned int), &flag)) {
144 if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
147 core_stats->entries = reg_data;
stats.c 120 unsigned int reg_data; local in function:mod_stats_create
136 &reg_data, sizeof(unsigned int), &flag))
137 core_stats->enabled = reg_data;
143 &reg_data, sizeof(unsigned int), &flag)) {
144 if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
147 core_stats->entries = reg_data;
stats.c 120 unsigned int reg_data; local in function:mod_stats_create
136 &reg_data, sizeof(unsigned int), &flag))
137 core_stats->enabled = reg_data;
143 &reg_data, sizeof(unsigned int), &flag)) {
144 if (reg_data > DAL_STATS_ENTRIES_REGKEY_MAX)
147 core_stats->entries = reg_data;
  /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_smu8_smumgr.c 183 uint32_t reg_data; local in function:smu8_load_mec_firmware
213 reg_data = lower_32_bits(info.mc_addr) &
215 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
217 reg_data = upper_32_bits(info.mc_addr) &
219 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
amdgpu_smu8_smumgr.c 183 uint32_t reg_data; local in function:smu8_load_mec_firmware
213 reg_data = lower_32_bits(info.mc_addr) &
215 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
217 reg_data = upper_32_bits(info.mc_addr) &
219 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
amdgpu_smu8_smumgr.c 183 uint32_t reg_data; local in function:smu8_load_mec_firmware
213 reg_data = lower_32_bits(info.mc_addr) &
215 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_LO, reg_data);
217 reg_data = upper_32_bits(info.mc_addr) &
219 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_HI, reg_data);
  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
edid.c 297 u32 reg_data = 0; local in function:gmbus3_mmio_read
310 reg_data |= (byte_data << (i << 3));
313 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
edid.c 297 u32 reg_data = 0; local in function:gmbus3_mmio_read
310 reg_data |= (byte_data << (i << 3));
313 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
edid.c 297 u32 reg_data = 0; local in function:gmbus3_mmio_read
310 reg_data |= (byte_data << (i << 3));
313 memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_vcn_v2_5.c 650 uint32_t reg_data = 0; local in function:vcn_v2_5_clock_gating_dpg_mode
654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
657 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
658 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
659 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1373 uint32_t reg_data = 0; local in function:vcn_v2_5_pause_dpg_mode
1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
1390 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
    [all...]
amdgpu_vcn_v2_5.c 650 uint32_t reg_data = 0; local in function:vcn_v2_5_clock_gating_dpg_mode
654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
657 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
658 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
659 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1373 uint32_t reg_data = 0; local in function:vcn_v2_5_pause_dpg_mode
1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
1390 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
    [all...]
amdgpu_vcn_v2_5.c 650 uint32_t reg_data = 0; local in function:vcn_v2_5_clock_gating_dpg_mode
654 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
657 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
658 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
659 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
680 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1373 uint32_t reg_data = 0; local in function:vcn_v2_5_pause_dpg_mode
1380 reg_data = RREG32_SOC15(UVD, inst_idx, mmUVD_DPG_PAUSE) &
1390 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
    [all...]
amdgpu_vcn_v1_0.c 638 uint32_t reg_data = 0; local in function:vcn_v1_0_clock_gating_dpg_mode
642 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
644 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
645 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
646 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
653 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
655 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
657 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
1212 uint32_t reg_data = 0; local in function:vcn_v1_0_pause_dpg_mode
    [all...]
amdgpu_vcn_v2_0.c 559 uint32_t reg_data = 0; local in function:vcn_v2_0_clock_gating_dpg_mode
563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
566 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
567 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
568 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1143 uint32_t reg_data = 0; local in function:vcn_v2_0_pause_dpg_mode
1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1160 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
    [all...]
amdgpu_vcn_v1_0.c 638 uint32_t reg_data = 0; local in function:vcn_v1_0_clock_gating_dpg_mode
642 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
644 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
645 reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
646 reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
647 WREG32_SOC15_DPG_MODE(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
653 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
655 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
656 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
657 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT
1212 uint32_t reg_data = 0; local in function:vcn_v1_0_pause_dpg_mode
    [all...]
amdgpu_vcn_v2_0.c 559 uint32_t reg_data = 0; local in function:vcn_v2_0_clock_gating_dpg_mode
563 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
565 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
566 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
567 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
568 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
589 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
1143 uint32_t reg_data = 0; local in function:vcn_v2_0_pause_dpg_mode
1150 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1160 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK
    [all...]

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