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    Searched defs:sdma0 (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_cik_sdma.c 91 * and gfx. There are two DMA engines (SDMA0, SDMA1)
313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
328 sdma0->sched.ready = false;
543 * Loads the sDMA0/1 ucode.
1082 /* sdma0 */
amdgpu_sdma_v2_4.c 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
347 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
352 if ((adev->mman.buffer_funcs_ring == sdma0) ||
364 sdma0->sched.ready = false;
976 /* sdma0 */
amdgpu_cik_sdma.c 91 * and gfx. There are two DMA engines (SDMA0, SDMA1)
313 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
318 if ((adev->mman.buffer_funcs_ring == sdma0) ||
328 sdma0->sched.ready = false;
543 * Loads the sDMA0/1 ucode.
1082 /* sdma0 */
amdgpu_sdma_v2_4.c 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
289 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
347 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
352 if ((adev->mman.buffer_funcs_ring == sdma0) ||
364 sdma0->sched.ready = false;
976 /* sdma0 */
amdgpu_sdma_v3_0.c 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
463 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
521 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
526 if ((adev->mman.buffer_funcs_ring == sdma0) ||
538 sdma0->sched.ready = false;
amdgpu_sdma_v5_0.c 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
495 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
500 if ((adev->mman.buffer_funcs_ring == sdma0) ||
513 sdma0->sched.ready = false;
787 * Loads the sDMA0/1 ucode.
1324 u32 sdma0, sdma1; local
1328 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1331 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
amdgpu_sdma_v3_0.c 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
463 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
521 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
526 if ((adev->mman.buffer_funcs_ring == sdma0) ||
538 sdma0->sched.ready = false;
amdgpu_sdma_v5_0.c 41 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
495 struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring; local
500 if ((adev->mman.buffer_funcs_ring == sdma0) ||
513 sdma0->sched.ready = false;
787 * Loads the sDMA0/1 ucode.
1324 u32 sdma0, sdma1; local
1328 sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1331 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)

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