| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/ |
| imx8mp.dtsi | 524 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
538 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
552 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
564 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
576 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
796 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mp.dtsi | 524 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
538 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
552 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
564 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
576 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
796 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mm.dtsi | 699 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
713 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
727 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
739 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
751 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
912 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mn.dtsi | 700 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
714 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
728 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
740 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
752 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
913 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mq.dtsi | 313 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
827 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
841 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
855 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
869 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
926 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>
1257 sdma1: sdma@30bd0000 { label
[all...] |
| imx8mm.dtsi | 699 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
713 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
727 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
739 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
751 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
912 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mn.dtsi | 700 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
714 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
728 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
740 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
752 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>
913 sdma1: dma-controller@30bd0000 { label in label:aips3
[all...] |
| imx8mq.dtsi | 313 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
827 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
841 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
855 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
869 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
926 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>
1257 sdma1: sdma@30bd0000 { label
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| amdgpu_cik_sdma.c | 91 * and gfx. There are two DMA engines (SDMA0, SDMA1)
314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:cik_sdma_gfx_stop
319 (adev->mman.buffer_funcs_ring == sdma1))
329 sdma1->sched.ready = false;
1089 /* sdma1 */
|
| amdgpu_sdma_v2_4.c | 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
348 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v2_4_gfx_stop
353 (adev->mman.buffer_funcs_ring == sdma1))
365 sdma1->sched.ready = false;
983 /* sdma1 */
|
| amdgpu_cik_sdma.c | 91 * and gfx. There are two DMA engines (SDMA0, SDMA1)
314 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:cik_sdma_gfx_stop
319 (adev->mman.buffer_funcs_ring == sdma1))
329 sdma1->sched.ready = false;
1089 /* sdma1 */
|
| amdgpu_sdma_v2_4.c | 90 * and gfx. There are two DMA engines (SDMA0, SDMA1)
291 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
348 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v2_4_gfx_stop
353 (adev->mman.buffer_funcs_ring == sdma1))
365 sdma1->sched.ready = false;
983 /* sdma1 */
|
| amdgpu_sdma_v3_0.c | 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
465 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
522 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v3_0_gfx_stop
527 (adev->mman.buffer_funcs_ring == sdma1))
539 sdma1->sched.ready = false;
|
| amdgpu_sdma_v5_0.c | 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
496 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v5_0_gfx_stop
501 (adev->mman.buffer_funcs_ring == sdma1))
514 sdma1->sched.ready = false;
1324 u32 sdma0, sdma1; local in function:sdma_v5_0_wait_for_idle
1329 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1331 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
|
| amdgpu_sdma_v3_0.c | 191 * and gfx. There are two DMA engines (SDMA0, SDMA1)
465 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
522 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v3_0_gfx_stop
527 (adev->mman.buffer_funcs_ring == sdma1))
539 sdma1->sched.ready = false;
|
| amdgpu_sdma_v5_0.c | 42 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
496 struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring; local in function:sdma_v5_0_gfx_stop
501 (adev->mman.buffer_funcs_ring == sdma1))
514 sdma1->sched.ready = false;
1324 u32 sdma0, sdma1; local in function:sdma_v5_0_wait_for_idle
1329 sdma1 = RREG32(sdma_v5_0_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1331 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
|
