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Searched defs:sq_hpc_write (Results 1 - 2 of 2) sorted by relevancy

/src/sys/arch/sgimips/hpc/
if_sq.c	132 #define sq_hpc_write(sc, off, val) \ macro 439 sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg); 440 sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg); 444 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0)); 447 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 455 sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF); 777 sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, 781 sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE); 794 sq_hpc_write(sc, HPC1_ENETX_NDBP, 796 sq_hpc_write(sc, HPC1_ENETX_CFXBP [all...]
if_sq.c	132 #define sq_hpc_write(sc, off, val) \ macro 439 sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg); 440 sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg); 444 sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0)); 447 sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 455 sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF); 777 sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc, 781 sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE); 794 sq_hpc_write(sc, HPC1_ENETX_NDBP, 796 sq_hpc_write(sc, HPC1_ENETX_CFXBP [all...]

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