| /src/sys/arch/evbarm/stand/bootimx23/ |
| emi_prep.c | 64 uint32_t tmp_r; local in function:emi_prep
69 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
70 tmp_r &= ~(HW_DRAM_CTL08_START | HW_DRAM_CTL08_SREFRESH);
71 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r);
76 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
77 tmp_r |= HW_DRAM_CTL08_START;
78 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r);
86 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16);
87 tmp_r |= (1 << 19);
88 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r);
[all...] |
| emi_prep.c | 64 uint32_t tmp_r; local in function:emi_prep
69 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
70 tmp_r &= ~(HW_DRAM_CTL08_START | HW_DRAM_CTL08_SREFRESH);
71 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r);
76 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08);
77 tmp_r |= HW_DRAM_CTL08_START;
78 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r);
86 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16);
87 tmp_r |= (1 << 19);
88 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r);
[all...] |
| clock_prep.c | 112 uint32_t tmp_r; local in function:set_hbus_div
117 tmp_r = REG_RD(CLKCTRL_HBUS);
118 tmp_r &= ~HW_CLKCTRL_HBUS_DIV;
119 tmp_r |= __SHIFTIN(div, HW_CLKCTRL_HBUS_DIV);
120 REG_WR(CLKCTRL_HBUS, tmp_r);
133 uint8_t tmp_r; local in function:set_cpu_frac
135 tmp_r = REG_RD_BYTE(CLKCTRL_FRAC);
136 tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATECPU | HW_CLKCTRL_FRAC_CPUFRAC);
137 tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_CPUFRAC);
138 REG_WR_BYTE(CLKCTRL_FRAC, tmp_r);
149 uint16_t tmp_r; local in function:set_emi_frac
168 uint32_t tmp_r; local in function:set_emi_div
187 uint32_t tmp_r; local in function:set_ssp_div
213 uint32_t tmp_r; local in function:set_io_frac
[all...] |
| clock_prep.c | 112 uint32_t tmp_r; local in function:set_hbus_div
117 tmp_r = REG_RD(CLKCTRL_HBUS);
118 tmp_r &= ~HW_CLKCTRL_HBUS_DIV;
119 tmp_r |= __SHIFTIN(div, HW_CLKCTRL_HBUS_DIV);
120 REG_WR(CLKCTRL_HBUS, tmp_r);
133 uint8_t tmp_r; local in function:set_cpu_frac
135 tmp_r = REG_RD_BYTE(CLKCTRL_FRAC);
136 tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATECPU | HW_CLKCTRL_FRAC_CPUFRAC);
137 tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_CPUFRAC);
138 REG_WR_BYTE(CLKCTRL_FRAC, tmp_r);
149 uint16_t tmp_r; local in function:set_emi_frac
168 uint32_t tmp_r; local in function:set_emi_div
187 uint32_t tmp_r; local in function:set_ssp_div
213 uint32_t tmp_r; local in function:set_io_frac
[all...] |
| power_prep.c | 94 uint32_t tmp_r; local in function:en_vbusvalid
96 tmp_r = REG_RD(PWR_5VCTRL);
97 tmp_r &= ~HW_POWER_5VCTRL_VBUSVALID_TRSH;
98 tmp_r |= __SHIFTIN(VBUSVALID_TRSH, HW_POWER_5VCTRL_VBUSVALID_TRSH);
99 REG_WR(PWR_5VCTRL, tmp_r);
125 uint32_t tmp_r; local in function:power_tune
137 tmp_r = REG_RD(PWR_DCLIMITS);
138 tmp_r &= ~HW_POWER_DCLIMITS_POSLIMIT_BUCK;
139 tmp_r |= __SHIFTIN(0x30, HW_POWER_DCLIMITS_POSLIMIT_BUCK);
140 REG_WR(PWR_DCLIMITS, tmp_r);
150 uint32_t tmp_r; local in function:en_4p2_reg
191 uint32_t tmp_r; local in function:en_4p2_to_dcdc
223 uint32_t tmp_r; local in function:power_vddd_from_dcdc
275 uint32_t tmp_r; local in function:power_vdda_from_dcdc
327 uint32_t tmp_r; local in function:power_vddio_from_dcdc
373 uint32_t tmp_r; local in function:power_vddmem
[all...] |
| power_prep.c | 94 uint32_t tmp_r; local in function:en_vbusvalid
96 tmp_r = REG_RD(PWR_5VCTRL);
97 tmp_r &= ~HW_POWER_5VCTRL_VBUSVALID_TRSH;
98 tmp_r |= __SHIFTIN(VBUSVALID_TRSH, HW_POWER_5VCTRL_VBUSVALID_TRSH);
99 REG_WR(PWR_5VCTRL, tmp_r);
125 uint32_t tmp_r; local in function:power_tune
137 tmp_r = REG_RD(PWR_DCLIMITS);
138 tmp_r &= ~HW_POWER_DCLIMITS_POSLIMIT_BUCK;
139 tmp_r |= __SHIFTIN(0x30, HW_POWER_DCLIMITS_POSLIMIT_BUCK);
140 REG_WR(PWR_DCLIMITS, tmp_r);
150 uint32_t tmp_r; local in function:en_4p2_reg
191 uint32_t tmp_r; local in function:en_4p2_to_dcdc
223 uint32_t tmp_r; local in function:power_vddd_from_dcdc
275 uint32_t tmp_r; local in function:power_vdda_from_dcdc
327 uint32_t tmp_r; local in function:power_vddio_from_dcdc
373 uint32_t tmp_r; local in function:power_vddmem
[all...] |
| /src/sys/arch/evbarm/imx23_olinuxino/ |
| imx23_olinuxino_machdep.c | 314 uint32_t tmp_r; local in function:power_vddio_from_dcdc
324 tmp_r = REG_RD(PWR_VDDIOCTRL);
325 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET;
326 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET);
327 REG_WR(PWR_VDDIOCTRL, tmp_r);
331 tmp_r = REG_RD(PWR_VDDIOCTRL);
332 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
333 REG_WR(PWR_VDDIOCTRL, tmp_r);
337 tmp_r = REG_RD(PWR_VDDIOCTRL);
338 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG)
362 uint32_t tmp_r; local in function:set_ssp_div
386 uint32_t tmp_r; local in function:set_io_frac
[all...] |
| imx23_olinuxino_machdep.c | 314 uint32_t tmp_r; local in function:power_vddio_from_dcdc
324 tmp_r = REG_RD(PWR_VDDIOCTRL);
325 tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET;
326 tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET);
327 REG_WR(PWR_VDDIOCTRL, tmp_r);
331 tmp_r = REG_RD(PWR_VDDIOCTRL);
332 tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
333 REG_WR(PWR_VDDIOCTRL, tmp_r);
337 tmp_r = REG_RD(PWR_VDDIOCTRL);
338 tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG)
362 uint32_t tmp_r; local in function:set_ssp_div
386 uint32_t tmp_r; local in function:set_io_frac
[all...] |
| /src/sys/external/bsd/sljit/dist/sljit_src/ |
| sljitNativePPC_common.c | 966 sljit_s32 tmp_r; local in function:getput_arg
975 tmp_r = ((inp_flags & LOAD_DATA) && ((inp_flags) & MEM_MASK) <= GPR_REG) ? reg : TMP_REG1;
977 if ((arg & REG_MASK) == tmp_r)
978 tmp_r = TMP_REG1;
986 tmp_r = TMP_REG3;
991 tmp_r = TMP_REG3;
994 FAIL_IF(push_inst(compiler, RLWINM | S(OFFS_REG(arg)) | A(tmp_r) | (argw << 11) | ((31 - argw) << 1)));
996 FAIL_IF(push_inst(compiler, RLDI(tmp_r, OFFS_REG(arg), argw, 63 - argw, 1)));
1001 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(tmp_r));
1025 tmp_r = arg
[all...] |
| sljitNativeARM_64.c | 925 sljit_s32 tmp_r, other_r; local in function:getput_arg
934 tmp_r = (flags & STORE) ? TMP_REG3 : reg;
990 FAIL_IF(push_inst(compiler, ADD | RD(tmp_r) | RN(arg) | RM(other_r) | ((argw & 0x3) << 10)));
991 return push_inst(compiler, sljit_mem_imm[flags & 0x3] | (shift << 30) | RT(reg) | RN(tmp_r));
1006 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(tmp_r) | RN(arg & REG_MASK) | ((argw >> 12) << 10)));
1008 | RT(reg) | RN(tmp_r) | ((argw & 0xfff) << (10 - shift)));
|
| sljitNativePPC_common.c | 966 sljit_s32 tmp_r; local in function:getput_arg
975 tmp_r = ((inp_flags & LOAD_DATA) && ((inp_flags) & MEM_MASK) <= GPR_REG) ? reg : TMP_REG1;
977 if ((arg & REG_MASK) == tmp_r)
978 tmp_r = TMP_REG1;
986 tmp_r = TMP_REG3;
991 tmp_r = TMP_REG3;
994 FAIL_IF(push_inst(compiler, RLWINM | S(OFFS_REG(arg)) | A(tmp_r) | (argw << 11) | ((31 - argw) << 1)));
996 FAIL_IF(push_inst(compiler, RLDI(tmp_r, OFFS_REG(arg), argw, 63 - argw, 1)));
1001 return push_inst(compiler, INST_CODE_AND_DST(inst, inp_flags, reg) | A(arg & REG_MASK) | B(tmp_r));
1025 tmp_r = arg
[all...] |
| sljitNativeARM_64.c | 925 sljit_s32 tmp_r, other_r; local in function:getput_arg
934 tmp_r = (flags & STORE) ? TMP_REG3 : reg;
990 FAIL_IF(push_inst(compiler, ADD | RD(tmp_r) | RN(arg) | RM(other_r) | ((argw & 0x3) << 10)));
991 return push_inst(compiler, sljit_mem_imm[flags & 0x3] | (shift << 30) | RT(reg) | RN(tmp_r));
1006 FAIL_IF(push_inst(compiler, ADDI | (1 << 22) | RD(tmp_r) | RN(arg & REG_MASK) | ((argw >> 12) << 10)));
1008 | RT(reg) | RN(tmp_r) | ((argw & 0xfff) << (10 - shift)));
|
