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    Searched defs:uartaddr (Results 1 - 25 of 64) sorted by relevancy

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/src/sys/arch/riscv/riscv/
mainbus.c	81 volatile uint8_t *uartaddr = cpu_earlydevice_va_p() ? local in function:com_platform_early_putchar 85 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 88 uartaddr[com_data] = c;
mainbus.c	81 volatile uint8_t *uartaddr = cpu_earlydevice_va_p() ? local in function:com_platform_early_putchar 85 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 88 uartaddr[com_data] = c;
mainbus.c	81 volatile uint8_t *uartaddr = cpu_earlydevice_va_p() ? local in function:com_platform_early_putchar 85 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 88 uartaddr[com_data] = c;
mainbus.c	81 volatile uint8_t *uartaddr = cpu_earlydevice_va_p() ? local in function:com_platform_early_putchar 85 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 88 uartaddr[com_data] = c;
/src/sys/arch/arm/fdt/
arm_platform.c	86 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:plcom_platform_early_putchar 90 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 93 uartaddr[PL01XCOM_DR / 4] = htole32(c); 96 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
arm_platform.c	86 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:plcom_platform_early_putchar 90 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 93 uartaddr[PL01XCOM_DR / 4] = htole32(c); 96 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
arm_platform.c	86 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:plcom_platform_early_putchar 90 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 93 uartaddr[PL01XCOM_DR / 4] = htole32(c); 96 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
arm_platform.c	86 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:plcom_platform_early_putchar 90 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 93 uartaddr[PL01XCOM_DR / 4] = htole32(c); 96 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
/src/sys/arch/arm/ti/
am3_platform.c	32 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:am33xx_platform_early_putchar 36 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 39 uartaddr[com_data] = htole32(c);
am3_platform.c	32 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:am33xx_platform_early_putchar 36 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 39 uartaddr[com_data] = htole32(c);
am3_platform.c	32 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:am33xx_platform_early_putchar 36 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 39 uartaddr[com_data] = htole32(c);
am3_platform.c	32 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:am33xx_platform_early_putchar 36 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 39 uartaddr[com_data] = htole32(c);
/src/sys/arch/arm/imx/
imx23_platform.c	70 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() local in function:imx23_platform_early_putchar 74 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 77 uartaddr[PL01XCOM_DR / 4] = htole32(c); 80 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
imx23_platform.c	70 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() local in function:imx23_platform_early_putchar 74 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 77 uartaddr[PL01XCOM_DR / 4] = htole32(c); 80 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
imx23_platform.c	70 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() local in function:imx23_platform_early_putchar 74 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 77 uartaddr[PL01XCOM_DR / 4] = htole32(c); 80 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
imx23_platform.c	70 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() local in function:imx23_platform_early_putchar 74 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFF) != 0) 77 uartaddr[PL01XCOM_DR / 4] = htole32(c); 80 while ((le32toh(uartaddr[PL01XCOM_FR / 4]) & PL01X_FR_TXFE) == 0)
/src/sys/arch/arm/altera/
cycv_platform.c	43 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:cycv_platform_early_putchar 47 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 50 uartaddr[com_data] = htole32(c);
cycv_platform.c	43 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:cycv_platform_early_putchar 47 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 50 uartaddr[com_data] = htole32(c);
cycv_platform.c	43 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:cycv_platform_early_putchar 47 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 50 uartaddr[com_data] = htole32(c);
cycv_platform.c	43 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:cycv_platform_early_putchar 47 while ((le32toh(uartaddr[com_lsr]) & LSR_TXRDY) == 0) 50 uartaddr[com_data] = htole32(c);
/src/sys/arch/arm/nvidia/
tegra_platform.c	79 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:tegra_platform_early_putchar 83 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 86 uartaddr[com_data] = c;
tegra_platform.c	79 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:tegra_platform_early_putchar 83 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 86 uartaddr[com_data] = c;
tegra_platform.c	79 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:tegra_platform_early_putchar 83 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 86 uartaddr[com_data] = c;
tegra_platform.c	79 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:tegra_platform_early_putchar 83 while ((uartaddr[com_lsr] & LSR_TXRDY) == 0) 86 uartaddr[com_data] = c;
/src/sys/arch/arm/nxp/
imx6_platform.c	121 volatile uint32_t *uartaddr = cpu_earlydevice_va_p() ? local in function:imx_platform_early_putchar 125 while ((le32toh(uartaddr[(IMX_USR2/4)]) & IMX_USR2_TXDC) == 0) 128 uartaddr[(IMX_UTXD/4)] = htole32(c);

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Indexes created Wed Nov 05 22:09:55 GMT 2025