| /src/sys/arch/sgimips/dev/ |
| dpclock.c | 94 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val) function in typeref:typename:void
154 writereg(sc, DP8573A_TIMESAVE_CTL, j);
155 writereg(sc, DP8573A_TIMESAVE_CTL, i);
204 writereg(sc, DP8573A_TIMESAVE_CTL, j);
205 writereg(sc, DP8573A_TIMESAVE_CTL, i);
223 writereg(sc, DP8573A_RT_MODE, j);
226 writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
228 writereg(sc, DP8573A_RT_MODE, i);
|
| dpclock.c | 94 writereg(struct dpclock_softc *sc, uint32_t reg, uint8_t val) function in typeref:typename:void
154 writereg(sc, DP8573A_TIMESAVE_CTL, j);
155 writereg(sc, DP8573A_TIMESAVE_CTL, i);
204 writereg(sc, DP8573A_TIMESAVE_CTL, j);
205 writereg(sc, DP8573A_TIMESAVE_CTL, i);
223 writereg(sc, DP8573A_RT_MODE, j);
226 writereg(sc, DP8573A_COUNTERS +i, regs[DP8573A_COUNTERS + i]);
228 writereg(sc, DP8573A_RT_MODE, i);
|
| /src/sys/arch/mips/ingenic/ |
| ingenic_regs.h | 119 writereg(uint32_t reg, uint32_t val) function in typeref:typename:void
404 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
405 writereg(reg + JZ_GPIO_MASKS, mask);
406 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */
416 writereg(reg, mask);
425 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
426 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
427 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
428 writereg(reg + JZ_GPIO_PAT0C, mask);
437 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio *
[all...] |
| ingenic_regs.h | 119 writereg(uint32_t reg, uint32_t val) function in typeref:typename:void
404 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
405 writereg(reg + JZ_GPIO_MASKS, mask);
406 writereg(reg + JZ_GPIO_PAT1C, mask); /* make output */
416 writereg(reg, mask);
425 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio */
426 writereg(reg + JZ_GPIO_MASKC, mask); /* device mode */
427 writereg(reg + JZ_GPIO_PAT1C, mask); /* select 0 */
428 writereg(reg + JZ_GPIO_PAT0C, mask);
437 writereg(reg + JZ_GPIO_INTC, mask); /* use as gpio *
[all...] |
