Searched refs:CLK_TOP_MSDC50_0_H_SEL (Results 1 - 5 of 5) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmt8173-clk.h107 #define CLK_TOP_MSDC50_0_H_SEL 95 macro
H A Dmediatek,mt6795-clk.h105 #define CLK_TOP_MSDC50_0_H_SEL 92 macro
H A Dmt8192-clk.h37 #define CLK_TOP_MSDC50_0_H_SEL 23 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt6795.dtsi683 <&topckgen CLK_TOP_MSDC50_0_H_SEL>,
H A Dmt8173.dtsi897 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;

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