1 /* $NetBSD: mt8192-clk.h,v 1.1.1.1 2021/11/07 16:50:00 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Chun-Jie Chen <chun-jie.chen (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT8192_H 10 #define _DT_BINDINGS_CLK_MT8192_H 11 12 /* TOPCKGEN */ 13 14 #define CLK_TOP_AXI_SEL 0 15 #define CLK_TOP_SPM_SEL 1 16 #define CLK_TOP_SCP_SEL 2 17 #define CLK_TOP_BUS_AXIMEM_SEL 3 18 #define CLK_TOP_DISP_SEL 4 19 #define CLK_TOP_MDP_SEL 5 20 #define CLK_TOP_IMG1_SEL 6 21 #define CLK_TOP_IMG2_SEL 7 22 #define CLK_TOP_IPE_SEL 8 23 #define CLK_TOP_DPE_SEL 9 24 #define CLK_TOP_CAM_SEL 10 25 #define CLK_TOP_CCU_SEL 11 26 #define CLK_TOP_DSP7_SEL 12 27 #define CLK_TOP_MFG_REF_SEL 13 28 #define CLK_TOP_MFG_PLL_SEL 14 29 #define CLK_TOP_CAMTG_SEL 15 30 #define CLK_TOP_CAMTG2_SEL 16 31 #define CLK_TOP_CAMTG3_SEL 17 32 #define CLK_TOP_CAMTG4_SEL 18 33 #define CLK_TOP_CAMTG5_SEL 19 34 #define CLK_TOP_CAMTG6_SEL 20 35 #define CLK_TOP_UART_SEL 21 36 #define CLK_TOP_SPI_SEL 22 37 #define CLK_TOP_MSDC50_0_H_SEL 23 38 #define CLK_TOP_MSDC50_0_SEL 24 39 #define CLK_TOP_MSDC30_1_SEL 25 40 #define CLK_TOP_MSDC30_2_SEL 26 41 #define CLK_TOP_AUDIO_SEL 27 42 #define CLK_TOP_AUD_INTBUS_SEL 28 43 #define CLK_TOP_PWRAP_ULPOSC_SEL 29 44 #define CLK_TOP_ATB_SEL 30 45 #define CLK_TOP_DPI_SEL 31 46 #define CLK_TOP_SCAM_SEL 32 47 #define CLK_TOP_DISP_PWM_SEL 33 48 #define CLK_TOP_USB_TOP_SEL 34 49 #define CLK_TOP_SSUSB_XHCI_SEL 35 50 #define CLK_TOP_I2C_SEL 36 51 #define CLK_TOP_SENINF_SEL 37 52 #define CLK_TOP_SENINF1_SEL 38 53 #define CLK_TOP_SENINF2_SEL 39 54 #define CLK_TOP_SENINF3_SEL 40 55 #define CLK_TOP_TL_SEL 41 56 #define CLK_TOP_DXCC_SEL 42 57 #define CLK_TOP_AUD_ENGEN1_SEL 43 58 #define CLK_TOP_AUD_ENGEN2_SEL 44 59 #define CLK_TOP_AES_UFSFDE_SEL 45 60 #define CLK_TOP_UFS_SEL 46 61 #define CLK_TOP_AUD_1_SEL 47 62 #define CLK_TOP_AUD_2_SEL 48 63 #define CLK_TOP_ADSP_SEL 49 64 #define CLK_TOP_DPMAIF_MAIN_SEL 50 65 #define CLK_TOP_VENC_SEL 51 66 #define CLK_TOP_VDEC_SEL 52 67 #define CLK_TOP_CAMTM_SEL 53 68 #define CLK_TOP_PWM_SEL 54 69 #define CLK_TOP_AUDIO_H_SEL 55 70 #define CLK_TOP_SPMI_MST_SEL 56 71 #define CLK_TOP_AES_MSDCFDE_SEL 57 72 #define CLK_TOP_SFLASH_SEL 58 73 #define CLK_TOP_APLL_I2S0_M_SEL 59 74 #define CLK_TOP_APLL_I2S1_M_SEL 60 75 #define CLK_TOP_APLL_I2S2_M_SEL 61 76 #define CLK_TOP_APLL_I2S3_M_SEL 62 77 #define CLK_TOP_APLL_I2S4_M_SEL 63 78 #define CLK_TOP_APLL_I2S5_M_SEL 64 79 #define CLK_TOP_APLL_I2S6_M_SEL 65 80 #define CLK_TOP_APLL_I2S7_M_SEL 66 81 #define CLK_TOP_APLL_I2S8_M_SEL 67 82 #define CLK_TOP_APLL_I2S9_M_SEL 68 83 #define CLK_TOP_MAINPLL_D3 69 84 #define CLK_TOP_MAINPLL_D4 70 85 #define CLK_TOP_MAINPLL_D4_D2 71 86 #define CLK_TOP_MAINPLL_D4_D4 72 87 #define CLK_TOP_MAINPLL_D4_D8 73 88 #define CLK_TOP_MAINPLL_D4_D16 74 89 #define CLK_TOP_MAINPLL_D5 75 90 #define CLK_TOP_MAINPLL_D5_D2 76 91 #define CLK_TOP_MAINPLL_D5_D4 77 92 #define CLK_TOP_MAINPLL_D5_D8 78 93 #define CLK_TOP_MAINPLL_D6 79 94 #define CLK_TOP_MAINPLL_D6_D2 80 95 #define CLK_TOP_MAINPLL_D6_D4 81 96 #define CLK_TOP_MAINPLL_D7 82 97 #define CLK_TOP_MAINPLL_D7_D2 83 98 #define CLK_TOP_MAINPLL_D7_D4 84 99 #define CLK_TOP_MAINPLL_D7_D8 85 100 #define CLK_TOP_UNIVPLL_D3 86 101 #define CLK_TOP_UNIVPLL_D4 87 102 #define CLK_TOP_UNIVPLL_D4_D2 88 103 #define CLK_TOP_UNIVPLL_D4_D4 89 104 #define CLK_TOP_UNIVPLL_D4_D8 90 105 #define CLK_TOP_UNIVPLL_D5 91 106 #define CLK_TOP_UNIVPLL_D5_D2 92 107 #define CLK_TOP_UNIVPLL_D5_D4 93 108 #define CLK_TOP_UNIVPLL_D5_D8 94 109 #define CLK_TOP_UNIVPLL_D6 95 110 #define CLK_TOP_UNIVPLL_D6_D2 96 111 #define CLK_TOP_UNIVPLL_D6_D4 97 112 #define CLK_TOP_UNIVPLL_D6_D8 98 113 #define CLK_TOP_UNIVPLL_D6_D16 99 114 #define CLK_TOP_UNIVPLL_D7 100 115 #define CLK_TOP_APLL1 101 116 #define CLK_TOP_APLL1_D2 102 117 #define CLK_TOP_APLL1_D4 103 118 #define CLK_TOP_APLL1_D8 104 119 #define CLK_TOP_APLL2 105 120 #define CLK_TOP_APLL2_D2 106 121 #define CLK_TOP_APLL2_D4 107 122 #define CLK_TOP_APLL2_D8 108 123 #define CLK_TOP_MMPLL_D4 109 124 #define CLK_TOP_MMPLL_D4_D2 110 125 #define CLK_TOP_MMPLL_D5 111 126 #define CLK_TOP_MMPLL_D5_D2 112 127 #define CLK_TOP_MMPLL_D6 113 128 #define CLK_TOP_MMPLL_D6_D2 114 129 #define CLK_TOP_MMPLL_D7 115 130 #define CLK_TOP_MMPLL_D9 116 131 #define CLK_TOP_APUPLL 117 132 #define CLK_TOP_NPUPLL 118 133 #define CLK_TOP_TVDPLL 119 134 #define CLK_TOP_TVDPLL_D2 120 135 #define CLK_TOP_TVDPLL_D4 121 136 #define CLK_TOP_TVDPLL_D8 122 137 #define CLK_TOP_TVDPLL_D16 123 138 #define CLK_TOP_MSDCPLL 124 139 #define CLK_TOP_MSDCPLL_D2 125 140 #define CLK_TOP_MSDCPLL_D4 126 141 #define CLK_TOP_ULPOSC 127 142 #define CLK_TOP_OSC_D2 128 143 #define CLK_TOP_OSC_D4 129 144 #define CLK_TOP_OSC_D8 130 145 #define CLK_TOP_OSC_D10 131 146 #define CLK_TOP_OSC_D16 132 147 #define CLK_TOP_OSC_D20 133 148 #define CLK_TOP_CSW_F26M_D2 134 149 #define CLK_TOP_ADSPPLL 135 150 #define CLK_TOP_UNIVPLL_192M 136 151 #define CLK_TOP_UNIVPLL_192M_D2 137 152 #define CLK_TOP_UNIVPLL_192M_D4 138 153 #define CLK_TOP_UNIVPLL_192M_D8 139 154 #define CLK_TOP_UNIVPLL_192M_D16 140 155 #define CLK_TOP_UNIVPLL_192M_D32 141 156 #define CLK_TOP_APLL12_DIV0 142 157 #define CLK_TOP_APLL12_DIV1 143 158 #define CLK_TOP_APLL12_DIV2 144 159 #define CLK_TOP_APLL12_DIV3 145 160 #define CLK_TOP_APLL12_DIV4 146 161 #define CLK_TOP_APLL12_DIVB 147 162 #define CLK_TOP_APLL12_DIV5 148 163 #define CLK_TOP_APLL12_DIV6 149 164 #define CLK_TOP_APLL12_DIV7 150 165 #define CLK_TOP_APLL12_DIV8 151 166 #define CLK_TOP_APLL12_DIV9 152 167 #define CLK_TOP_SSUSB_TOP_REF 153 168 #define CLK_TOP_SSUSB_PHY_REF 154 169 #define CLK_TOP_NR_CLK 155 170 171 /* INFRACFG */ 172 173 #define CLK_INFRA_PMIC_TMR 0 174 #define CLK_INFRA_PMIC_AP 1 175 #define CLK_INFRA_PMIC_MD 2 176 #define CLK_INFRA_PMIC_CONN 3 177 #define CLK_INFRA_SCPSYS 4 178 #define CLK_INFRA_SEJ 5 179 #define CLK_INFRA_APXGPT 6 180 #define CLK_INFRA_GCE 7 181 #define CLK_INFRA_GCE2 8 182 #define CLK_INFRA_THERM 9 183 #define CLK_INFRA_I2C0 10 184 #define CLK_INFRA_AP_DMA_PSEUDO 11 185 #define CLK_INFRA_I2C2 12 186 #define CLK_INFRA_I2C3 13 187 #define CLK_INFRA_PWM_H 14 188 #define CLK_INFRA_PWM1 15 189 #define CLK_INFRA_PWM2 16 190 #define CLK_INFRA_PWM3 17 191 #define CLK_INFRA_PWM4 18 192 #define CLK_INFRA_PWM 19 193 #define CLK_INFRA_UART0 20 194 #define CLK_INFRA_UART1 21 195 #define CLK_INFRA_UART2 22 196 #define CLK_INFRA_UART3 23 197 #define CLK_INFRA_GCE_26M 24 198 #define CLK_INFRA_CQ_DMA_FPC 25 199 #define CLK_INFRA_BTIF 26 200 #define CLK_INFRA_SPI0 27 201 #define CLK_INFRA_MSDC0 28 202 #define CLK_INFRA_MSDC1 29 203 #define CLK_INFRA_MSDC2 30 204 #define CLK_INFRA_MSDC0_SRC 31 205 #define CLK_INFRA_GCPU 32 206 #define CLK_INFRA_TRNG 33 207 #define CLK_INFRA_AUXADC 34 208 #define CLK_INFRA_CPUM 35 209 #define CLK_INFRA_CCIF1_AP 36 210 #define CLK_INFRA_CCIF1_MD 37 211 #define CLK_INFRA_AUXADC_MD 38 212 #define CLK_INFRA_PCIE_TL_26M 39 213 #define CLK_INFRA_MSDC1_SRC 40 214 #define CLK_INFRA_MSDC2_SRC 41 215 #define CLK_INFRA_PCIE_TL_96M 42 216 #define CLK_INFRA_PCIE_PL_P_250M 43 217 #define CLK_INFRA_DEVICE_APC 44 218 #define CLK_INFRA_CCIF_AP 45 219 #define CLK_INFRA_DEBUGSYS 46 220 #define CLK_INFRA_AUDIO 47 221 #define CLK_INFRA_CCIF_MD 48 222 #define CLK_INFRA_DXCC_SEC_CORE 49 223 #define CLK_INFRA_DXCC_AO 50 224 #define CLK_INFRA_DBG_TRACE 51 225 #define CLK_INFRA_DEVMPU_B 52 226 #define CLK_INFRA_DRAMC_F26M 53 227 #define CLK_INFRA_IRTX 54 228 #define CLK_INFRA_SSUSB 55 229 #define CLK_INFRA_DISP_PWM 56 230 #define CLK_INFRA_CLDMA_B 57 231 #define CLK_INFRA_AUDIO_26M_B 58 232 #define CLK_INFRA_MODEM_TEMP_SHARE 59 233 #define CLK_INFRA_SPI1 60 234 #define CLK_INFRA_I2C4 61 235 #define CLK_INFRA_SPI2 62 236 #define CLK_INFRA_SPI3 63 237 #define CLK_INFRA_UNIPRO_SYS 64 238 #define CLK_INFRA_UNIPRO_TICK 65 239 #define CLK_INFRA_UFS_MP_SAP_B 66 240 #define CLK_INFRA_MD32_B 67 241 #define CLK_INFRA_UNIPRO_MBIST 68 242 #define CLK_INFRA_I2C5 69 243 #define CLK_INFRA_I2C5_ARBITER 70 244 #define CLK_INFRA_I2C5_IMM 71 245 #define CLK_INFRA_I2C1_ARBITER 72 246 #define CLK_INFRA_I2C1_IMM 73 247 #define CLK_INFRA_I2C2_ARBITER 74 248 #define CLK_INFRA_I2C2_IMM 75 249 #define CLK_INFRA_SPI4 76 250 #define CLK_INFRA_SPI5 77 251 #define CLK_INFRA_CQ_DMA 78 252 #define CLK_INFRA_UFS 79 253 #define CLK_INFRA_AES_UFSFDE 80 254 #define CLK_INFRA_UFS_TICK 81 255 #define CLK_INFRA_SSUSB_XHCI 82 256 #define CLK_INFRA_MSDC0_SELF 83 257 #define CLK_INFRA_MSDC1_SELF 84 258 #define CLK_INFRA_MSDC2_SELF 85 259 #define CLK_INFRA_UFS_AXI 86 260 #define CLK_INFRA_I2C6 87 261 #define CLK_INFRA_AP_MSDC0 88 262 #define CLK_INFRA_MD_MSDC0 89 263 #define CLK_INFRA_CCIF5_AP 90 264 #define CLK_INFRA_CCIF5_MD 91 265 #define CLK_INFRA_PCIE_TOP_H_133M 92 266 #define CLK_INFRA_FLASHIF_TOP_H_133M 93 267 #define CLK_INFRA_PCIE_PERI_26M 94 268 #define CLK_INFRA_CCIF2_AP 95 269 #define CLK_INFRA_CCIF2_MD 96 270 #define CLK_INFRA_CCIF3_AP 97 271 #define CLK_INFRA_CCIF3_MD 98 272 #define CLK_INFRA_SEJ_F13M 99 273 #define CLK_INFRA_AES 100 274 #define CLK_INFRA_I2C7 101 275 #define CLK_INFRA_I2C8 102 276 #define CLK_INFRA_FBIST2FPC 103 277 #define CLK_INFRA_DEVICE_APC_SYNC 104 278 #define CLK_INFRA_DPMAIF_MAIN 105 279 #define CLK_INFRA_PCIE_TL_32K 106 280 #define CLK_INFRA_CCIF4_AP 107 281 #define CLK_INFRA_CCIF4_MD 108 282 #define CLK_INFRA_SPI6 109 283 #define CLK_INFRA_SPI7 110 284 #define CLK_INFRA_133M 111 285 #define CLK_INFRA_66M 112 286 #define CLK_INFRA_66M_PERI_BUS 113 287 #define CLK_INFRA_FREE_DCM_133M 114 288 #define CLK_INFRA_FREE_DCM_66M 115 289 #define CLK_INFRA_PERI_BUS_DCM_133M 116 290 #define CLK_INFRA_PERI_BUS_DCM_66M 117 291 #define CLK_INFRA_FLASHIF_PERI_26M 118 292 #define CLK_INFRA_FLASHIF_SFLASH 119 293 #define CLK_INFRA_AP_DMA 120 294 #define CLK_INFRA_NR_CLK 121 295 296 /* PERICFG */ 297 298 #define CLK_PERI_PERIAXI 0 299 #define CLK_PERI_NR_CLK 1 300 301 /* APMIXEDSYS */ 302 303 #define CLK_APMIXED_MAINPLL 0 304 #define CLK_APMIXED_UNIVPLL 1 305 #define CLK_APMIXED_USBPLL 2 306 #define CLK_APMIXED_MSDCPLL 3 307 #define CLK_APMIXED_MMPLL 4 308 #define CLK_APMIXED_ADSPPLL 5 309 #define CLK_APMIXED_MFGPLL 6 310 #define CLK_APMIXED_TVDPLL 7 311 #define CLK_APMIXED_APLL1 8 312 #define CLK_APMIXED_APLL2 9 313 #define CLK_APMIXED_MIPID26M 10 314 #define CLK_APMIXED_NR_CLK 11 315 316 /* SCP_ADSP */ 317 318 #define CLK_SCP_ADSP_AUDIODSP 0 319 #define CLK_SCP_ADSP_NR_CLK 1 320 321 /* IMP_IIC_WRAP_C */ 322 323 #define CLK_IMP_IIC_WRAP_C_I2C10 0 324 #define CLK_IMP_IIC_WRAP_C_I2C11 1 325 #define CLK_IMP_IIC_WRAP_C_I2C12 2 326 #define CLK_IMP_IIC_WRAP_C_I2C13 3 327 #define CLK_IMP_IIC_WRAP_C_NR_CLK 4 328 329 /* AUDSYS */ 330 331 #define CLK_AUD_AFE 0 332 #define CLK_AUD_22M 1 333 #define CLK_AUD_24M 2 334 #define CLK_AUD_APLL2_TUNER 3 335 #define CLK_AUD_APLL_TUNER 4 336 #define CLK_AUD_TDM 5 337 #define CLK_AUD_ADC 6 338 #define CLK_AUD_DAC 7 339 #define CLK_AUD_DAC_PREDIS 8 340 #define CLK_AUD_TML 9 341 #define CLK_AUD_NLE 10 342 #define CLK_AUD_I2S1_B 11 343 #define CLK_AUD_I2S2_B 12 344 #define CLK_AUD_I2S3_B 13 345 #define CLK_AUD_I2S4_B 14 346 #define CLK_AUD_CONNSYS_I2S_ASRC 15 347 #define CLK_AUD_GENERAL1_ASRC 16 348 #define CLK_AUD_GENERAL2_ASRC 17 349 #define CLK_AUD_DAC_HIRES 18 350 #define CLK_AUD_ADC_HIRES 19 351 #define CLK_AUD_ADC_HIRES_TML 20 352 #define CLK_AUD_ADDA6_ADC 21 353 #define CLK_AUD_ADDA6_ADC_HIRES 22 354 #define CLK_AUD_3RD_DAC 23 355 #define CLK_AUD_3RD_DAC_PREDIS 24 356 #define CLK_AUD_3RD_DAC_TML 25 357 #define CLK_AUD_3RD_DAC_HIRES 26 358 #define CLK_AUD_I2S5_B 27 359 #define CLK_AUD_I2S6_B 28 360 #define CLK_AUD_I2S7_B 29 361 #define CLK_AUD_I2S8_B 30 362 #define CLK_AUD_I2S9_B 31 363 #define CLK_AUD_NR_CLK 32 364 365 /* IMP_IIC_WRAP_E */ 366 367 #define CLK_IMP_IIC_WRAP_E_I2C3 0 368 #define CLK_IMP_IIC_WRAP_E_NR_CLK 1 369 370 /* IMP_IIC_WRAP_S */ 371 372 #define CLK_IMP_IIC_WRAP_S_I2C7 0 373 #define CLK_IMP_IIC_WRAP_S_I2C8 1 374 #define CLK_IMP_IIC_WRAP_S_I2C9 2 375 #define CLK_IMP_IIC_WRAP_S_NR_CLK 3 376 377 /* IMP_IIC_WRAP_WS */ 378 379 #define CLK_IMP_IIC_WRAP_WS_I2C1 0 380 #define CLK_IMP_IIC_WRAP_WS_I2C2 1 381 #define CLK_IMP_IIC_WRAP_WS_I2C4 2 382 #define CLK_IMP_IIC_WRAP_WS_NR_CLK 3 383 384 /* IMP_IIC_WRAP_W */ 385 386 #define CLK_IMP_IIC_WRAP_W_I2C5 0 387 #define CLK_IMP_IIC_WRAP_W_NR_CLK 1 388 389 /* IMP_IIC_WRAP_N */ 390 391 #define CLK_IMP_IIC_WRAP_N_I2C0 0 392 #define CLK_IMP_IIC_WRAP_N_I2C6 1 393 #define CLK_IMP_IIC_WRAP_N_NR_CLK 2 394 395 /* MSDC_TOP */ 396 397 #define CLK_MSDC_TOP_AES_0P 0 398 #define CLK_MSDC_TOP_SRC_0P 1 399 #define CLK_MSDC_TOP_SRC_1P 2 400 #define CLK_MSDC_TOP_SRC_2P 3 401 #define CLK_MSDC_TOP_P_MSDC0 4 402 #define CLK_MSDC_TOP_P_MSDC1 5 403 #define CLK_MSDC_TOP_P_MSDC2 6 404 #define CLK_MSDC_TOP_P_CFG 7 405 #define CLK_MSDC_TOP_AXI 8 406 #define CLK_MSDC_TOP_H_MST_0P 9 407 #define CLK_MSDC_TOP_H_MST_1P 10 408 #define CLK_MSDC_TOP_H_MST_2P 11 409 #define CLK_MSDC_TOP_MEM_OFF_DLY_26M 12 410 #define CLK_MSDC_TOP_32K 13 411 #define CLK_MSDC_TOP_AHB2AXI_BRG_AXI 14 412 #define CLK_MSDC_TOP_NR_CLK 15 413 414 /* MSDC */ 415 416 #define CLK_MSDC_AXI_WRAP 0 417 #define CLK_MSDC_NR_CLK 1 418 419 /* MFGCFG */ 420 421 #define CLK_MFG_BG3D 0 422 #define CLK_MFG_NR_CLK 1 423 424 /* MMSYS */ 425 426 #define CLK_MM_DISP_MUTEX0 0 427 #define CLK_MM_DISP_CONFIG 1 428 #define CLK_MM_DISP_OVL0 2 429 #define CLK_MM_DISP_RDMA0 3 430 #define CLK_MM_DISP_OVL0_2L 4 431 #define CLK_MM_DISP_WDMA0 5 432 #define CLK_MM_DISP_UFBC_WDMA0 6 433 #define CLK_MM_DISP_RSZ0 7 434 #define CLK_MM_DISP_AAL0 8 435 #define CLK_MM_DISP_CCORR0 9 436 #define CLK_MM_DISP_DITHER0 10 437 #define CLK_MM_SMI_INFRA 11 438 #define CLK_MM_DISP_GAMMA0 12 439 #define CLK_MM_DISP_POSTMASK0 13 440 #define CLK_MM_DISP_DSC_WRAP0 14 441 #define CLK_MM_DSI0 15 442 #define CLK_MM_DISP_COLOR0 16 443 #define CLK_MM_SMI_COMMON 17 444 #define CLK_MM_DISP_FAKE_ENG0 18 445 #define CLK_MM_DISP_FAKE_ENG1 19 446 #define CLK_MM_MDP_TDSHP4 20 447 #define CLK_MM_MDP_RSZ4 21 448 #define CLK_MM_MDP_AAL4 22 449 #define CLK_MM_MDP_HDR4 23 450 #define CLK_MM_MDP_RDMA4 24 451 #define CLK_MM_MDP_COLOR4 25 452 #define CLK_MM_DISP_Y2R0 26 453 #define CLK_MM_SMI_GALS 27 454 #define CLK_MM_DISP_OVL2_2L 28 455 #define CLK_MM_DISP_RDMA4 29 456 #define CLK_MM_DISP_DPI0 30 457 #define CLK_MM_SMI_IOMMU 31 458 #define CLK_MM_DSI_DSI0 32 459 #define CLK_MM_DPI_DPI0 33 460 #define CLK_MM_26MHZ 34 461 #define CLK_MM_32KHZ 35 462 #define CLK_MM_NR_CLK 36 463 464 /* IMGSYS */ 465 466 #define CLK_IMG_LARB9 0 467 #define CLK_IMG_LARB10 1 468 #define CLK_IMG_DIP 2 469 #define CLK_IMG_GALS 3 470 #define CLK_IMG_NR_CLK 4 471 472 /* IMGSYS2 */ 473 474 #define CLK_IMG2_LARB11 0 475 #define CLK_IMG2_LARB12 1 476 #define CLK_IMG2_MFB 2 477 #define CLK_IMG2_WPE 3 478 #define CLK_IMG2_MSS 4 479 #define CLK_IMG2_GALS 5 480 #define CLK_IMG2_NR_CLK 6 481 482 /* VDECSYS_SOC */ 483 484 #define CLK_VDEC_SOC_LARB1 0 485 #define CLK_VDEC_SOC_LAT 1 486 #define CLK_VDEC_SOC_LAT_ACTIVE 2 487 #define CLK_VDEC_SOC_VDEC 3 488 #define CLK_VDEC_SOC_VDEC_ACTIVE 4 489 #define CLK_VDEC_SOC_NR_CLK 5 490 491 /* VDECSYS */ 492 493 #define CLK_VDEC_LARB1 0 494 #define CLK_VDEC_LAT 1 495 #define CLK_VDEC_LAT_ACTIVE 2 496 #define CLK_VDEC_VDEC 3 497 #define CLK_VDEC_ACTIVE 4 498 #define CLK_VDEC_NR_CLK 5 499 500 /* VENCSYS */ 501 502 #define CLK_VENC_SET0_LARB 0 503 #define CLK_VENC_SET1_VENC 1 504 #define CLK_VENC_SET2_JPGENC 2 505 #define CLK_VENC_SET5_GALS 3 506 #define CLK_VENC_NR_CLK 4 507 508 /* CAMSYS */ 509 510 #define CLK_CAM_LARB13 0 511 #define CLK_CAM_DFP_VAD 1 512 #define CLK_CAM_LARB14 2 513 #define CLK_CAM_CAM 3 514 #define CLK_CAM_CAMTG 4 515 #define CLK_CAM_SENINF 5 516 #define CLK_CAM_CAMSV0 6 517 #define CLK_CAM_CAMSV1 7 518 #define CLK_CAM_CAMSV2 8 519 #define CLK_CAM_CAMSV3 9 520 #define CLK_CAM_CCU0 10 521 #define CLK_CAM_CCU1 11 522 #define CLK_CAM_MRAW0 12 523 #define CLK_CAM_FAKE_ENG 13 524 #define CLK_CAM_CCU_GALS 14 525 #define CLK_CAM_CAM2MM_GALS 15 526 #define CLK_CAM_NR_CLK 16 527 528 /* CAMSYS_RAWA */ 529 530 #define CLK_CAM_RAWA_LARBX 0 531 #define CLK_CAM_RAWA_CAM 1 532 #define CLK_CAM_RAWA_CAMTG 2 533 #define CLK_CAM_RAWA_NR_CLK 3 534 535 /* CAMSYS_RAWB */ 536 537 #define CLK_CAM_RAWB_LARBX 0 538 #define CLK_CAM_RAWB_CAM 1 539 #define CLK_CAM_RAWB_CAMTG 2 540 #define CLK_CAM_RAWB_NR_CLK 3 541 542 /* CAMSYS_RAWC */ 543 544 #define CLK_CAM_RAWC_LARBX 0 545 #define CLK_CAM_RAWC_CAM 1 546 #define CLK_CAM_RAWC_CAMTG 2 547 #define CLK_CAM_RAWC_NR_CLK 3 548 549 /* IPESYS */ 550 551 #define CLK_IPE_LARB19 0 552 #define CLK_IPE_LARB20 1 553 #define CLK_IPE_SMI_SUBCOM 2 554 #define CLK_IPE_FD 3 555 #define CLK_IPE_FE 4 556 #define CLK_IPE_RSC 5 557 #define CLK_IPE_DPE 6 558 #define CLK_IPE_GALS 7 559 #define CLK_IPE_NR_CLK 8 560 561 /* MDPSYS */ 562 563 #define CLK_MDP_RDMA0 0 564 #define CLK_MDP_TDSHP0 1 565 #define CLK_MDP_IMG_DL_ASYNC0 2 566 #define CLK_MDP_IMG_DL_ASYNC1 3 567 #define CLK_MDP_RDMA1 4 568 #define CLK_MDP_TDSHP1 5 569 #define CLK_MDP_SMI0 6 570 #define CLK_MDP_APB_BUS 7 571 #define CLK_MDP_WROT0 8 572 #define CLK_MDP_RSZ0 9 573 #define CLK_MDP_HDR0 10 574 #define CLK_MDP_MUTEX0 11 575 #define CLK_MDP_WROT1 12 576 #define CLK_MDP_RSZ1 13 577 #define CLK_MDP_HDR1 14 578 #define CLK_MDP_FAKE_ENG0 15 579 #define CLK_MDP_AAL0 16 580 #define CLK_MDP_AAL1 17 581 #define CLK_MDP_COLOR0 18 582 #define CLK_MDP_COLOR1 19 583 #define CLK_MDP_IMG_DL_RELAY0_ASYNC0 20 584 #define CLK_MDP_IMG_DL_RELAY1_ASYNC1 21 585 #define CLK_MDP_NR_CLK 22 586 587 #endif /* _DT_BINDINGS_CLK_MT8192_H */ 588
Indexes created Mon Sep 29 15:09:53 GMT 2025