Searched refs:CLK_VDO1_HDR_VDO_FE0_DL_ASYNC (Results 1 - 3 of 3) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h714 #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 49 macro
H A Dmt8195-clk.h852 #define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 38 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi3553 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,

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