1/* $NetBSD: mediatek,mt8188-clk.h,v 1.1.1.1 2026/01/18 05:21:32 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Garmin Chang <garmin.chang@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_MT8188_H 10#define _DT_BINDINGS_CLK_MT8188_H 11 12/* TOPCKGEN */ 13#define CLK_TOP_AXI 0 14#define CLK_TOP_SPM 1 15#define CLK_TOP_SCP 2 16#define CLK_TOP_BUS_AXIMEM 3 17#define CLK_TOP_VPP 4 18#define CLK_TOP_ETHDR 5 19#define CLK_TOP_IPE 6 20#define CLK_TOP_CAM 7 21#define CLK_TOP_CCU 8 22#define CLK_TOP_CCU_AHB 9 23#define CLK_TOP_IMG 10 24#define CLK_TOP_CAMTM 11 25#define CLK_TOP_DSP 12 26#define CLK_TOP_DSP1 13 27#define CLK_TOP_DSP2 14 28#define CLK_TOP_DSP3 15 29#define CLK_TOP_DSP4 16 30#define CLK_TOP_DSP5 17 31#define CLK_TOP_DSP6 18 32#define CLK_TOP_DSP7 19 33#define CLK_TOP_MFG_CORE_TMP 20 34#define CLK_TOP_CAMTG 21 35#define CLK_TOP_CAMTG2 22 36#define CLK_TOP_CAMTG3 23 37#define CLK_TOP_UART 24 38#define CLK_TOP_SPI 25 39#define CLK_TOP_MSDC50_0_HCLK 26 40#define CLK_TOP_MSDC50_0 27 41#define CLK_TOP_MSDC30_1 28 42#define CLK_TOP_MSDC30_2 29 43#define CLK_TOP_INTDIR 30 44#define CLK_TOP_AUD_INTBUS 31 45#define CLK_TOP_AUDIO_H 32 46#define CLK_TOP_PWRAP_ULPOSC 33 47#define CLK_TOP_ATB 34 48#define CLK_TOP_SSPM 35 49#define CLK_TOP_DP 36 50#define CLK_TOP_EDP 37 51#define CLK_TOP_DPI 38 52#define CLK_TOP_DISP_PWM0 39 53#define CLK_TOP_DISP_PWM1 40 54#define CLK_TOP_USB_TOP 41 55#define CLK_TOP_SSUSB_XHCI 42 56#define CLK_TOP_USB_TOP_2P 43 57#define CLK_TOP_SSUSB_XHCI_2P 44 58#define CLK_TOP_USB_TOP_3P 45 59#define CLK_TOP_SSUSB_XHCI_3P 46 60#define CLK_TOP_I2C 47 61#define CLK_TOP_SENINF 48 62#define CLK_TOP_SENINF1 49 63#define CLK_TOP_GCPU 50 64#define CLK_TOP_VENC 51 65#define CLK_TOP_VDEC 52 66#define CLK_TOP_PWM 53 67#define CLK_TOP_MCUPM 54 68#define CLK_TOP_SPMI_P_MST 55 69#define CLK_TOP_SPMI_M_MST 56 70#define CLK_TOP_DVFSRC 57 71#define CLK_TOP_TL 58 72#define CLK_TOP_AES_MSDCFDE 59 73#define CLK_TOP_DSI_OCC 60 74#define CLK_TOP_WPE_VPP 61 75#define CLK_TOP_HDCP 62 76#define CLK_TOP_HDCP_24M 63 77#define CLK_TOP_HDMI_APB 64 78#define CLK_TOP_SNPS_ETH_250M 65 79#define CLK_TOP_SNPS_ETH_62P4M_PTP 66 80#define CLK_TOP_SNPS_ETH_50M_RMII 67 81#define CLK_TOP_ADSP 68 82#define CLK_TOP_AUDIO_LOCAL_BUS 69 83#define CLK_TOP_ASM_H 70 84#define CLK_TOP_ASM_L 71 85#define CLK_TOP_APLL1 72 86#define CLK_TOP_APLL2 73 87#define CLK_TOP_APLL3 74 88#define CLK_TOP_APLL4 75 89#define CLK_TOP_APLL5 76 90#define CLK_TOP_I2SO1 77 91#define CLK_TOP_I2SO2 78 92#define CLK_TOP_I2SI1 79 93#define CLK_TOP_I2SI2 80 94#define CLK_TOP_DPTX 81 95#define CLK_TOP_AUD_IEC 82 96#define CLK_TOP_A1SYS_HP 83 97#define CLK_TOP_A2SYS 84 98#define CLK_TOP_A3SYS 85 99#define CLK_TOP_A4SYS 86 100#define CLK_TOP_ECC 87 101#define CLK_TOP_SPINOR 88 102#define CLK_TOP_ULPOSC 89 103#define CLK_TOP_SRCK 90 104#define CLK_TOP_MFG_CK_FAST_REF 91 105#define CLK_TOP_MAINPLL_D3 92 106#define CLK_TOP_MAINPLL_D4 93 107#define CLK_TOP_MAINPLL_D4_D2 94 108#define CLK_TOP_MAINPLL_D4_D4 95 109#define CLK_TOP_MAINPLL_D4_D8 96 110#define CLK_TOP_MAINPLL_D5 97 111#define CLK_TOP_MAINPLL_D5_D2 98 112#define CLK_TOP_MAINPLL_D5_D4 99 113#define CLK_TOP_MAINPLL_D5_D8 100 114#define CLK_TOP_MAINPLL_D6 101 115#define CLK_TOP_MAINPLL_D6_D2 102 116#define CLK_TOP_MAINPLL_D6_D4 103 117#define CLK_TOP_MAINPLL_D6_D8 104 118#define CLK_TOP_MAINPLL_D7 105 119#define CLK_TOP_MAINPLL_D7_D2 106 120#define CLK_TOP_MAINPLL_D7_D4 107 121#define CLK_TOP_MAINPLL_D7_D8 108 122#define CLK_TOP_MAINPLL_D9 109 123#define CLK_TOP_UNIVPLL_D2 110 124#define CLK_TOP_UNIVPLL_D3 111 125#define CLK_TOP_UNIVPLL_D4 112 126#define CLK_TOP_UNIVPLL_D4_D2 113 127#define CLK_TOP_UNIVPLL_D4_D4 114 128#define CLK_TOP_UNIVPLL_D4_D8 115 129#define CLK_TOP_UNIVPLL_D5 116 130#define CLK_TOP_UNIVPLL_D5_D2 117 131#define CLK_TOP_UNIVPLL_D5_D4 118 132#define CLK_TOP_UNIVPLL_D5_D8 119 133#define CLK_TOP_UNIVPLL_D6 120 134#define CLK_TOP_UNIVPLL_D6_D2 121 135#define CLK_TOP_UNIVPLL_D6_D4 122 136#define CLK_TOP_UNIVPLL_D6_D8 123 137#define CLK_TOP_UNIVPLL_D7 124 138#define CLK_TOP_UNIVPLL_192M 125 139#define CLK_TOP_UNIVPLL_192M_D4 126 140#define CLK_TOP_UNIVPLL_192M_D8 127 141#define CLK_TOP_UNIVPLL_192M_D10 128 142#define CLK_TOP_UNIVPLL_192M_D16 129 143#define CLK_TOP_UNIVPLL_192M_D32 130 144#define CLK_TOP_APLL1_D3 131 145#define CLK_TOP_APLL1_D4 132 146#define CLK_TOP_APLL2_D3 133 147#define CLK_TOP_APLL2_D4 134 148#define CLK_TOP_APLL3_D4 135 149#define CLK_TOP_APLL4_D4 136 150#define CLK_TOP_APLL5_D4 137 151#define CLK_TOP_MMPLL_D4 138 152#define CLK_TOP_MMPLL_D4_D2 139 153#define CLK_TOP_MMPLL_D5 140 154#define CLK_TOP_MMPLL_D5_D2 141 155#define CLK_TOP_MMPLL_D5_D4 142 156#define CLK_TOP_MMPLL_D6 143 157#define CLK_TOP_MMPLL_D6_D2 144 158#define CLK_TOP_MMPLL_D7 145 159#define CLK_TOP_MMPLL_D9 146 160#define CLK_TOP_TVDPLL1 147 161#define CLK_TOP_TVDPLL1_D2 148 162#define CLK_TOP_TVDPLL1_D4 149 163#define CLK_TOP_TVDPLL1_D8 150 164#define CLK_TOP_TVDPLL1_D16 151 165#define CLK_TOP_TVDPLL2 152 166#define CLK_TOP_TVDPLL2_D2 153 167#define CLK_TOP_TVDPLL2_D4 154 168#define CLK_TOP_TVDPLL2_D8 155 169#define CLK_TOP_TVDPLL2_D16 156 170#define CLK_TOP_MSDCPLL_D2 157 171#define CLK_TOP_MSDCPLL_D16 158 172#define CLK_TOP_ETHPLL 159 173#define CLK_TOP_ETHPLL_D2 160 174#define CLK_TOP_ETHPLL_D4 161 175#define CLK_TOP_ETHPLL_D8 162 176#define CLK_TOP_ETHPLL_D10 163 177#define CLK_TOP_ADSPPLL_D2 164 178#define CLK_TOP_ADSPPLL_D4 165 179#define CLK_TOP_ADSPPLL_D8 166 180#define CLK_TOP_ULPOSC1 167 181#define CLK_TOP_ULPOSC1_D2 168 182#define CLK_TOP_ULPOSC1_D4 169 183#define CLK_TOP_ULPOSC1_D8 170 184#define CLK_TOP_ULPOSC1_D7 171 185#define CLK_TOP_ULPOSC1_D10 172 186#define CLK_TOP_ULPOSC1_D16 173 187#define CLK_TOP_MPHONE_SLAVE_BCK 174 188#define CLK_TOP_PAD_FPC 175 189#define CLK_TOP_466M_FMEM 176 190#define CLK_TOP_PEXTP_PIPE 177 191#define CLK_TOP_DSI_PHY 178 192#define CLK_TOP_APLL12_CK_DIV0 179 193#define CLK_TOP_APLL12_CK_DIV1 180 194#define CLK_TOP_APLL12_CK_DIV2 181 195#define CLK_TOP_APLL12_CK_DIV3 182 196#define CLK_TOP_APLL12_CK_DIV4 183 197#define CLK_TOP_APLL12_CK_DIV9 184 198#define CLK_TOP_CFGREG_CLOCK_EN_VPP0 185 199#define CLK_TOP_CFGREG_CLOCK_EN_VPP1 186 200#define CLK_TOP_CFGREG_CLOCK_EN_VDO0 187 201#define CLK_TOP_CFGREG_CLOCK_EN_VDO1 188 202#define CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS 189 203#define CLK_TOP_CFGREG_F26M_VPP0 190 204#define CLK_TOP_CFGREG_F26M_VPP1 191 205#define CLK_TOP_CFGREG_F26M_VDO0 192 206#define CLK_TOP_CFGREG_F26M_VDO1 193 207#define CLK_TOP_CFGREG_AUD_F26M_AUD 194 208#define CLK_TOP_CFGREG_UNIPLL_SES 195 209#define CLK_TOP_CFGREG_F_PCIE_PHY_REF 196 210#define CLK_TOP_SSUSB_TOP_REF 197 211#define CLK_TOP_SSUSB_PHY_REF 198 212#define CLK_TOP_SSUSB_TOP_P1_REF 199 213#define CLK_TOP_SSUSB_PHY_P1_REF 200 214#define CLK_TOP_SSUSB_TOP_P2_REF 201 215#define CLK_TOP_SSUSB_PHY_P2_REF 202 216#define CLK_TOP_SSUSB_TOP_P3_REF 203 217#define CLK_TOP_SSUSB_PHY_P3_REF 204 218#define CLK_TOP_NR_CLK 205 219 220/* INFRACFG_AO */ 221#define CLK_INFRA_AO_PMIC_TMR 0 222#define CLK_INFRA_AO_PMIC_AP 1 223#define CLK_INFRA_AO_PMIC_MD 2 224#define CLK_INFRA_AO_PMIC_CONN 3 225#define CLK_INFRA_AO_SEJ 4 226#define CLK_INFRA_AO_APXGPT 5 227#define CLK_INFRA_AO_GCE 6 228#define CLK_INFRA_AO_GCE2 7 229#define CLK_INFRA_AO_THERM 8 230#define CLK_INFRA_AO_PWM_HCLK 9 231#define CLK_INFRA_AO_PWM1 10 232#define CLK_INFRA_AO_PWM2 11 233#define CLK_INFRA_AO_PWM3 12 234#define CLK_INFRA_AO_PWM4 13 235#define CLK_INFRA_AO_PWM 14 236#define CLK_INFRA_AO_UART0 15 237#define CLK_INFRA_AO_UART1 16 238#define CLK_INFRA_AO_UART2 17 239#define CLK_INFRA_AO_UART3 18 240#define CLK_INFRA_AO_UART4 19 241#define CLK_INFRA_AO_GCE_26M 20 242#define CLK_INFRA_AO_CQ_DMA_FPC 21 243#define CLK_INFRA_AO_UART5 22 244#define CLK_INFRA_AO_HDMI_26M 23 245#define CLK_INFRA_AO_SPI0 24 246#define CLK_INFRA_AO_MSDC0 25 247#define CLK_INFRA_AO_MSDC1 26 248#define CLK_INFRA_AO_MSDC2 27 249#define CLK_INFRA_AO_MSDC0_SRC 28 250#define CLK_INFRA_AO_DVFSRC 29 251#define CLK_INFRA_AO_TRNG 30 252#define CLK_INFRA_AO_AUXADC 31 253#define CLK_INFRA_AO_CPUM 32 254#define CLK_INFRA_AO_HDMI_32K 33 255#define CLK_INFRA_AO_CEC_66M_HCLK 34 256#define CLK_INFRA_AO_PCIE_TL_26M 35 257#define CLK_INFRA_AO_MSDC1_SRC 36 258#define CLK_INFRA_AO_CEC_66M_BCLK 37 259#define CLK_INFRA_AO_PCIE_TL_96M 38 260#define CLK_INFRA_AO_DEVICE_APC 39 261#define CLK_INFRA_AO_ECC_66M_HCLK 40 262#define CLK_INFRA_AO_DEBUGSYS 41 263#define CLK_INFRA_AO_AUDIO 42 264#define CLK_INFRA_AO_PCIE_TL_32K 43 265#define CLK_INFRA_AO_DBG_TRACE 44 266#define CLK_INFRA_AO_DRAMC_F26M 45 267#define CLK_INFRA_AO_IRTX 46 268#define CLK_INFRA_AO_DISP_PWM 47 269#define CLK_INFRA_AO_CLDMA_BCLK 48 270#define CLK_INFRA_AO_AUDIO_26M_BCLK 49 271#define CLK_INFRA_AO_SPI1 50 272#define CLK_INFRA_AO_SPI2 51 273#define CLK_INFRA_AO_SPI3 52 274#define CLK_INFRA_AO_FSSPM 53 275#define CLK_INFRA_AO_SSPM_BUS_HCLK 54 276#define CLK_INFRA_AO_APDMA_BCLK 55 277#define CLK_INFRA_AO_SPI4 56 278#define CLK_INFRA_AO_SPI5 57 279#define CLK_INFRA_AO_CQ_DMA 58 280#define CLK_INFRA_AO_MSDC0_SELF 59 281#define CLK_INFRA_AO_MSDC1_SELF 60 282#define CLK_INFRA_AO_MSDC2_SELF 61 283#define CLK_INFRA_AO_I2S_DMA 62 284#define CLK_INFRA_AO_AP_MSDC0 63 285#define CLK_INFRA_AO_MD_MSDC0 64 286#define CLK_INFRA_AO_MSDC30_2 65 287#define CLK_INFRA_AO_GCPU 66 288#define CLK_INFRA_AO_PCIE_PERI_26M 67 289#define CLK_INFRA_AO_GCPU_66M_BCLK 68 290#define CLK_INFRA_AO_GCPU_133M_BCLK 69 291#define CLK_INFRA_AO_DISP_PWM1 70 292#define CLK_INFRA_AO_FBIST2FPC 71 293#define CLK_INFRA_AO_DEVICE_APC_SYNC 72 294#define CLK_INFRA_AO_PCIE_P1_PERI_26M 73 295#define CLK_INFRA_AO_133M_MCLK_CK 74 296#define CLK_INFRA_AO_66M_MCLK_CK 75 297#define CLK_INFRA_AO_PCIE_PL_P_250M_P0 76 298#define CLK_INFRA_AO_RG_AES_MSDCFDE_CK_0P 77 299#define CLK_INFRA_AO_NR_CLK 78 300 301/* APMIXEDSYS */ 302#define CLK_APMIXED_ETHPLL 0 303#define CLK_APMIXED_MSDCPLL 1 304#define CLK_APMIXED_TVDPLL1 2 305#define CLK_APMIXED_TVDPLL2 3 306#define CLK_APMIXED_MMPLL 4 307#define CLK_APMIXED_MAINPLL 5 308#define CLK_APMIXED_IMGPLL 6 309#define CLK_APMIXED_UNIVPLL 7 310#define CLK_APMIXED_ADSPPLL 8 311#define CLK_APMIXED_APLL1 9 312#define CLK_APMIXED_APLL2 10 313#define CLK_APMIXED_APLL3 11 314#define CLK_APMIXED_APLL4 12 315#define CLK_APMIXED_APLL5 13 316#define CLK_APMIXED_MFGPLL 14 317#define CLK_APMIXED_PLL_SSUSB26M_EN 15 318#define CLK_APMIXED_NR_CLK 16 319 320/* AUDIODSP */ 321#define CLK_AUDIODSP_AUDIO26M 0 322#define CLK_AUDIODSP_NR_CLK 1 323 324/* PERICFG_AO */ 325#define CLK_PERI_AO_ETHERNET 0 326#define CLK_PERI_AO_ETHERNET_BUS 1 327#define CLK_PERI_AO_FLASHIF_BUS 2 328#define CLK_PERI_AO_FLASHIF_26M 3 329#define CLK_PERI_AO_FLASHIFLASHCK 4 330#define CLK_PERI_AO_SSUSB_2P_BUS 5 331#define CLK_PERI_AO_SSUSB_2P_XHCI 6 332#define CLK_PERI_AO_SSUSB_3P_BUS 7 333#define CLK_PERI_AO_SSUSB_3P_XHCI 8 334#define CLK_PERI_AO_SSUSB_BUS 9 335#define CLK_PERI_AO_SSUSB_XHCI 10 336#define CLK_PERI_AO_ETHERNET_MAC 11 337#define CLK_PERI_AO_PCIE_P0_FMEM 12 338#define CLK_PERI_AO_NR_CLK 13 339 340/* IMP_IIC_WRAP_C */ 341#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C0 0 342#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C2 1 343#define CLK_IMP_IIC_WRAP_C_AP_CLOCK_I2C3 2 344#define CLK_IMP_IIC_WRAP_C_NR_CLK 3 345 346/* IMP_IIC_WRAP_W */ 347#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C1 0 348#define CLK_IMP_IIC_WRAP_W_AP_CLOCK_I2C4 1 349#define CLK_IMP_IIC_WRAP_W_NR_CLK 2 350 351/* IMP_IIC_WRAP_EN */ 352#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C5 0 353#define CLK_IMP_IIC_WRAP_EN_AP_CLOCK_I2C6 1 354#define CLK_IMP_IIC_WRAP_EN_NR_CLK 2 355 356/* MFGCFG */ 357#define CLK_MFGCFG_BG3D 0 358#define CLK_MFGCFG_NR_CLK 1 359 360/* VPPSYS0 */ 361#define CLK_VPP0_MDP_FG 0 362#define CLK_VPP0_STITCH 1 363#define CLK_VPP0_PADDING 2 364#define CLK_VPP0_MDP_TCC 3 365#define CLK_VPP0_WARP0_ASYNC_TX 4 366#define CLK_VPP0_WARP1_ASYNC_TX 5 367#define CLK_VPP0_MUTEX 6 368#define CLK_VPP02VPP1_RELAY 7 369#define CLK_VPP0_VPP12VPP0_ASYNC 8 370#define CLK_VPP0_MMSYSRAM_TOP 9 371#define CLK_VPP0_MDP_AAL 10 372#define CLK_VPP0_MDP_RSZ 11 373#define CLK_VPP0_SMI_COMMON_MMSRAM 12 374#define CLK_VPP0_GALS_VDO0_LARB0_MMSRAM 13 375#define CLK_VPP0_GALS_VDO0_LARB1_MMSRAM 14 376#define CLK_VPP0_GALS_VENCSYS_MMSRAM 15 377#define CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM 16 378#define CLK_VPP0_GALS_INFRA_MMSRAM 17 379#define CLK_VPP0_GALS_CAMSYS_MMSRAM 18 380#define CLK_VPP0_GALS_VPP1_LARB5_MMSRAM 19 381#define CLK_VPP0_GALS_VPP1_LARB6_MMSRAM 20 382#define CLK_VPP0_SMI_REORDER_MMSRAM 21 383#define CLK_VPP0_SMI_IOMMU 22 384#define CLK_VPP0_GALS_IMGSYS_CAMSYS 23 385#define CLK_VPP0_MDP_RDMA 24 386#define CLK_VPP0_MDP_WROT 25 387#define CLK_VPP0_GALS_EMI0_EMI1 26 388#define CLK_VPP0_SMI_SUB_COMMON_REORDER 27 389#define CLK_VPP0_SMI_RSI 28 390#define CLK_VPP0_SMI_COMMON_LARB4 29 391#define CLK_VPP0_GALS_VDEC_VDEC_CORE1 30 392#define CLK_VPP0_GALS_VPP1_WPESYS 31 393#define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 394#define CLK_VPP0_FAKE_ENG 33 395#define CLK_VPP0_MDP_HDR 34 396#define CLK_VPP0_MDP_TDSHP 35 397#define CLK_VPP0_MDP_COLOR 36 398#define CLK_VPP0_MDP_OVL 37 399#define CLK_VPP0_DSIP_RDMA 38 400#define CLK_VPP0_DISP_WDMA 39 401#define CLK_VPP0_MDP_HMS 40 402#define CLK_VPP0_WARP0_RELAY 41 403#define CLK_VPP0_WARP0_ASYNC 42 404#define CLK_VPP0_WARP1_RELAY 43 405#define CLK_VPP0_WARP1_ASYNC 44 406#define CLK_VPP0_NR_CLK 45 407 408/* WPESYS */ 409#define CLK_WPE_TOP_WPE_VPP0 0 410#define CLK_WPE_TOP_SMI_LARB7 1 411#define CLK_WPE_TOP_WPESYS_EVENT_TX 2 412#define CLK_WPE_TOP_SMI_LARB7_PCLK_EN 3 413#define CLK_WPE_TOP_NR_CLK 4 414 415/* WPESYS_VPP0 */ 416#define CLK_WPE_VPP0_VECI 0 417#define CLK_WPE_VPP0_VEC2I 1 418#define CLK_WPE_VPP0_VEC3I 2 419#define CLK_WPE_VPP0_WPEO 3 420#define CLK_WPE_VPP0_MSKO 4 421#define CLK_WPE_VPP0_VGEN 5 422#define CLK_WPE_VPP0_EXT 6 423#define CLK_WPE_VPP0_VFC 7 424#define CLK_WPE_VPP0_CACH0_TOP 8 425#define CLK_WPE_VPP0_CACH0_DMA 9 426#define CLK_WPE_VPP0_CACH1_TOP 10 427#define CLK_WPE_VPP0_CACH1_DMA 11 428#define CLK_WPE_VPP0_CACH2_TOP 12 429#define CLK_WPE_VPP0_CACH2_DMA 13 430#define CLK_WPE_VPP0_CACH3_TOP 14 431#define CLK_WPE_VPP0_CACH3_DMA 15 432#define CLK_WPE_VPP0_PSP 16 433#define CLK_WPE_VPP0_PSP2 17 434#define CLK_WPE_VPP0_SYNC 18 435#define CLK_WPE_VPP0_C24 19 436#define CLK_WPE_VPP0_MDP_CROP 20 437#define CLK_WPE_VPP0_ISP_CROP 21 438#define CLK_WPE_VPP0_TOP 22 439#define CLK_WPE_VPP0_NR_CLK 23 440 441/* VPPSYS1 */ 442#define CLK_VPP1_SVPP1_MDP_OVL 0 443#define CLK_VPP1_SVPP1_MDP_TCC 1 444#define CLK_VPP1_SVPP1_MDP_WROT 2 445#define CLK_VPP1_SVPP1_VPP_PAD 3 446#define CLK_VPP1_SVPP2_MDP_WROT 4 447#define CLK_VPP1_SVPP2_VPP_PAD 5 448#define CLK_VPP1_SVPP3_MDP_WROT 6 449#define CLK_VPP1_SVPP3_VPP_PAD 7 450#define CLK_VPP1_SVPP1_MDP_RDMA 8 451#define CLK_VPP1_SVPP1_MDP_FG 9 452#define CLK_VPP1_SVPP2_MDP_RDMA 10 453#define CLK_VPP1_SVPP2_MDP_FG 11 454#define CLK_VPP1_SVPP3_MDP_RDMA 12 455#define CLK_VPP1_SVPP3_MDP_FG 13 456#define CLK_VPP1_VPP_SPLIT 14 457#define CLK_VPP1_SVPP2_VDO0_DL_RELAY 15 458#define CLK_VPP1_SVPP1_MDP_RSZ 16 459#define CLK_VPP1_SVPP1_MDP_TDSHP 17 460#define CLK_VPP1_SVPP1_MDP_COLOR 18 461#define CLK_VPP1_SVPP3_VDO1_DL_RELAY 19 462#define CLK_VPP1_SVPP2_MDP_RSZ 20 463#define CLK_VPP1_SVPP2_VPP_MERGE 21 464#define CLK_VPP1_SVPP2_MDP_TDSHP 22 465#define CLK_VPP1_SVPP2_MDP_COLOR 23 466#define CLK_VPP1_SVPP3_MDP_RSZ 24 467#define CLK_VPP1_SVPP3_VPP_MERGE 25 468#define CLK_VPP1_SVPP3_MDP_TDSHP 26 469#define CLK_VPP1_SVPP3_MDP_COLOR 27 470#define CLK_VPP1_GALS5 28 471#define CLK_VPP1_GALS6 29 472#define CLK_VPP1_LARB5 30 473#define CLK_VPP1_LARB6 31 474#define CLK_VPP1_SVPP1_MDP_HDR 32 475#define CLK_VPP1_SVPP1_MDP_AAL 33 476#define CLK_VPP1_SVPP2_MDP_HDR 34 477#define CLK_VPP1_SVPP2_MDP_AAL 35 478#define CLK_VPP1_SVPP3_MDP_HDR 36 479#define CLK_VPP1_SVPP3_MDP_AAL 37 480#define CLK_VPP1_DISP_MUTEX 38 481#define CLK_VPP1_SVPP2_VDO1_DL_RELAY 39 482#define CLK_VPP1_SVPP3_VDO0_DL_RELAY 40 483#define CLK_VPP1_VPP0_DL_ASYNC 41 484#define CLK_VPP1_VPP0_DL1_RELAY 42 485#define CLK_VPP1_LARB5_FAKE_ENG 43 486#define CLK_VPP1_LARB6_FAKE_ENG 44 487#define CLK_VPP1_HDMI_META 45 488#define CLK_VPP1_VPP_SPLIT_HDMI 46 489#define CLK_VPP1_DGI_IN 47 490#define CLK_VPP1_DGI_OUT 48 491#define CLK_VPP1_VPP_SPLIT_DGI 49 492#define CLK_VPP1_DL_CON_OCC 50 493#define CLK_VPP1_VPP_SPLIT_26M 51 494#define CLK_VPP1_NR_CLK 52 495 496/* IMGSYS */ 497#define CLK_IMGSYS_MAIN_LARB9 0 498#define CLK_IMGSYS_MAIN_TRAW0 1 499#define CLK_IMGSYS_MAIN_TRAW1 2 500#define CLK_IMGSYS_MAIN_VCORE_GALS 3 501#define CLK_IMGSYS_MAIN_DIP0 4 502#define CLK_IMGSYS_MAIN_WPE0 5 503#define CLK_IMGSYS_MAIN_IPE 6 504#define CLK_IMGSYS_MAIN_WPE1 7 505#define CLK_IMGSYS_MAIN_WPE2 8 506#define CLK_IMGSYS_MAIN_GALS 9 507#define CLK_IMGSYS_MAIN_NR_CLK 10 508 509/* IMGSYS1_DIP_TOP */ 510#define CLK_IMGSYS1_DIP_TOP_LARB10 0 511#define CLK_IMGSYS1_DIP_TOP_DIP_TOP 1 512#define CLK_IMGSYS1_DIP_TOP_NR_CLK 2 513 514/* IMGSYS1_DIP_NR */ 515#define CLK_IMGSYS1_DIP_NR_LARB15 0 516#define CLK_IMGSYS1_DIP_NR_DIP_NR 1 517#define CLK_IMGSYS1_DIP_NR_NR_CLK 2 518 519/* IMGSYS_WPE1 */ 520#define CLK_IMGSYS_WPE1_LARB11 0 521#define CLK_IMGSYS_WPE1 1 522#define CLK_IMGSYS_WPE1_NR_CLK 2 523 524/* IPESYS */ 525#define CLK_IPE_DPE 0 526#define CLK_IPE_FDVT 1 527#define CLK_IPE_ME 2 528#define CLK_IPESYS_TOP 3 529#define CLK_IPE_SMI_LARB12 4 530#define CLK_IPE_NR_CLK 5 531 532/* IMGSYS_WPE2 */ 533#define CLK_IMGSYS_WPE2_LARB11 0 534#define CLK_IMGSYS_WPE2 1 535#define CLK_IMGSYS_WPE2_NR_CLK 2 536 537/* IMGSYS_WPE3 */ 538#define CLK_IMGSYS_WPE3_LARB11 0 539#define CLK_IMGSYS_WPE3 1 540#define CLK_IMGSYS_WPE3_NR_CLK 2 541 542/* CAMSYS */ 543#define CLK_CAM_MAIN_LARB13 0 544#define CLK_CAM_MAIN_LARB14 1 545#define CLK_CAM_MAIN_CAM 2 546#define CLK_CAM_MAIN_CAM_SUBA 3 547#define CLK_CAM_MAIN_CAM_SUBB 4 548#define CLK_CAM_MAIN_CAMTG 5 549#define CLK_CAM_MAIN_SENINF 6 550#define CLK_CAM_MAIN_GCAMSVA 7 551#define CLK_CAM_MAIN_GCAMSVB 8 552#define CLK_CAM_MAIN_GCAMSVC 9 553#define CLK_CAM_MAIN_GCAMSVD 10 554#define CLK_CAM_MAIN_GCAMSVE 11 555#define CLK_CAM_MAIN_GCAMSVF 12 556#define CLK_CAM_MAIN_GCAMSVG 13 557#define CLK_CAM_MAIN_GCAMSVH 14 558#define CLK_CAM_MAIN_GCAMSVI 15 559#define CLK_CAM_MAIN_GCAMSVJ 16 560#define CLK_CAM_MAIN_CAMSV_TOP 17 561#define CLK_CAM_MAIN_CAMSV_CQ_A 18 562#define CLK_CAM_MAIN_CAMSV_CQ_B 19 563#define CLK_CAM_MAIN_CAMSV_CQ_C 20 564#define CLK_CAM_MAIN_FAKE_ENG 21 565#define CLK_CAM_MAIN_CAM2MM0_GALS 22 566#define CLK_CAM_MAIN_CAM2MM1_GALS 23 567#define CLK_CAM_MAIN_CAM2SYS_GALS 24 568#define CLK_CAM_MAIN_NR_CLK 25 569 570/* CAMSYS_RAWA */ 571#define CLK_CAM_RAWA_LARBX 0 572#define CLK_CAM_RAWA_CAM 1 573#define CLK_CAM_RAWA_CAMTG 2 574#define CLK_CAM_RAWA_NR_CLK 3 575 576/* CAMSYS_YUVA */ 577#define CLK_CAM_YUVA_LARBX 0 578#define CLK_CAM_YUVA_CAM 1 579#define CLK_CAM_YUVA_CAMTG 2 580#define CLK_CAM_YUVA_NR_CLK 3 581 582/* CAMSYS_RAWB */ 583#define CLK_CAM_RAWB_LARBX 0 584#define CLK_CAM_RAWB_CAM 1 585#define CLK_CAM_RAWB_CAMTG 2 586#define CLK_CAM_RAWB_NR_CLK 3 587 588/* CAMSYS_YUVB */ 589#define CLK_CAM_YUVB_LARBX 0 590#define CLK_CAM_YUVB_CAM 1 591#define CLK_CAM_YUVB_CAMTG 2 592#define CLK_CAM_YUVB_NR_CLK 3 593 594/* CCUSYS */ 595#define CLK_CCU_LARB27 0 596#define CLK_CCU_AHB 1 597#define CLK_CCU_CCU0 2 598#define CLK_CCU_NR_CLK 3 599 600/* VDECSYS_SOC */ 601#define CLK_VDEC1_SOC_LARB1 0 602#define CLK_VDEC1_SOC_LAT 1 603#define CLK_VDEC1_SOC_LAT_ACTIVE 2 604#define CLK_VDEC1_SOC_LAT_ENG 3 605#define CLK_VDEC1_SOC_VDEC 4 606#define CLK_VDEC1_SOC_VDEC_ACTIVE 5 607#define CLK_VDEC1_SOC_VDEC_ENG 6 608#define CLK_VDEC1_NR_CLK 7 609 610/* VDECSYS */ 611#define CLK_VDEC2_LARB1 0 612#define CLK_VDEC2_LAT 1 613#define CLK_VDEC2_VDEC 2 614#define CLK_VDEC2_VDEC_ACTIVE 3 615#define CLK_VDEC2_VDEC_ENG 4 616#define CLK_VDEC2_NR_CLK 5 617 618/* VENCSYS */ 619#define CLK_VENC1_LARB 0 620#define CLK_VENC1_VENC 1 621#define CLK_VENC1_JPGENC 2 622#define CLK_VENC1_JPGDEC 3 623#define CLK_VENC1_JPGDEC_C1 4 624#define CLK_VENC1_GALS 5 625#define CLK_VENC1_GALS_SRAM 6 626#define CLK_VENC1_NR_CLK 7 627 628/* VDOSYS0 */ 629#define CLK_VDO0_DISP_OVL0 0 630#define CLK_VDO0_FAKE_ENG0 1 631#define CLK_VDO0_DISP_CCORR0 2 632#define CLK_VDO0_DISP_MUTEX0 3 633#define CLK_VDO0_DISP_GAMMA0 4 634#define CLK_VDO0_DISP_DITHER0 5 635#define CLK_VDO0_DISP_WDMA0 6 636#define CLK_VDO0_DISP_RDMA0 7 637#define CLK_VDO0_DSI0 8 638#define CLK_VDO0_DSI1 9 639#define CLK_VDO0_DSC_WRAP0 10 640#define CLK_VDO0_VPP_MERGE0 11 641#define CLK_VDO0_DP_INTF0 12 642#define CLK_VDO0_DISP_AAL0 13 643#define CLK_VDO0_INLINEROT0 14 644#define CLK_VDO0_APB_BUS 15 645#define CLK_VDO0_DISP_COLOR0 16 646#define CLK_VDO0_MDP_WROT0 17 647#define CLK_VDO0_DISP_RSZ0 18 648#define CLK_VDO0_DISP_POSTMASK0 19 649#define CLK_VDO0_FAKE_ENG1 20 650#define CLK_VDO0_DL_ASYNC2 21 651#define CLK_VDO0_DL_RELAY3 22 652#define CLK_VDO0_DL_RELAY4 23 653#define CLK_VDO0_SMI_GALS 24 654#define CLK_VDO0_SMI_COMMON 25 655#define CLK_VDO0_SMI_EMI 26 656#define CLK_VDO0_SMI_IOMMU 27 657#define CLK_VDO0_SMI_LARB 28 658#define CLK_VDO0_SMI_RSI 29 659#define CLK_VDO0_DSI0_DSI 30 660#define CLK_VDO0_DSI1_DSI 31 661#define CLK_VDO0_DP_INTF0_DP_INTF 32 662#define CLK_VDO0_NR_CLK 33 663 664/* VDOSYS1 */ 665#define CLK_VDO1_SMI_LARB2 0 666#define CLK_VDO1_SMI_LARB3 1 667#define CLK_VDO1_GALS 2 668#define CLK_VDO1_FAKE_ENG0 3 669#define CLK_VDO1_FAKE_ENG1 4 670#define CLK_VDO1_MDP_RDMA0 5 671#define CLK_VDO1_MDP_RDMA1 6 672#define CLK_VDO1_MDP_RDMA2 7 673#define CLK_VDO1_MDP_RDMA3 8 674#define CLK_VDO1_VPP_MERGE0 9 675#define CLK_VDO1_VPP_MERGE1 10 676#define CLK_VDO1_VPP_MERGE2 11 677#define CLK_VDO1_VPP_MERGE3 12 678#define CLK_VDO1_VPP_MERGE4 13 679#define CLK_VDO1_VPP2_TO_VDO1_DL_ASYNC 14 680#define CLK_VDO1_VPP3_TO_VDO1_DL_ASYNC 15 681#define CLK_VDO1_DISP_MUTEX 16 682#define CLK_VDO1_MDP_RDMA4 17 683#define CLK_VDO1_MDP_RDMA5 18 684#define CLK_VDO1_MDP_RDMA6 19 685#define CLK_VDO1_MDP_RDMA7 20 686#define CLK_VDO1_DP_INTF0_MMCK 21 687#define CLK_VDO1_DPI0_MM 22 688#define CLK_VDO1_DPI1_MM 23 689#define CLK_VDO1_MERGE0_DL_ASYNC 24 690#define CLK_VDO1_MERGE1_DL_ASYNC 25 691#define CLK_VDO1_MERGE2_DL_ASYNC 26 692#define CLK_VDO1_MERGE3_DL_ASYNC 27 693#define CLK_VDO1_MERGE4_DL_ASYNC 28 694#define CLK_VDO1_DSC_VDO1_DL_ASYNC 29 695#define CLK_VDO1_MERGE_VDO1_DL_ASYNC 30 696#define CLK_VDO1_PADDING0 31 697#define CLK_VDO1_PADDING1 32 698#define CLK_VDO1_PADDING2 33 699#define CLK_VDO1_PADDING3 34 700#define CLK_VDO1_PADDING4 35 701#define CLK_VDO1_PADDING5 36 702#define CLK_VDO1_PADDING6 37 703#define CLK_VDO1_PADDING7 38 704#define CLK_VDO1_DISP_RSZ0 39 705#define CLK_VDO1_DISP_RSZ1 40 706#define CLK_VDO1_DISP_RSZ2 41 707#define CLK_VDO1_DISP_RSZ3 42 708#define CLK_VDO1_HDR_VDO_FE0 43 709#define CLK_VDO1_HDR_GFX_FE0 44 710#define CLK_VDO1_HDR_VDO_BE 45 711#define CLK_VDO1_HDR_VDO_FE1 46 712#define CLK_VDO1_HDR_GFX_FE1 47 713#define CLK_VDO1_DISP_MIXER 48 714#define CLK_VDO1_HDR_VDO_FE0_DL_ASYNC 49 715#define CLK_VDO1_HDR_VDO_FE1_DL_ASYNC 50 716#define CLK_VDO1_HDR_GFX_FE0_DL_ASYNC 51 717#define CLK_VDO1_HDR_GFX_FE1_DL_ASYNC 52 718#define CLK_VDO1_HDR_VDO_BE_DL_ASYNC 53 719#define CLK_VDO1_DPI0 54 720#define CLK_VDO1_DISP_MONITOR_DPI0 55 721#define CLK_VDO1_DPI1 56 722#define CLK_VDO1_DISP_MONITOR_DPI1 57 723#define CLK_VDO1_DPINTF 58 724#define CLK_VDO1_DISP_MONITOR_DPINTF 59 725#define CLK_VDO1_26M_SLOW 60 726#define CLK_VDO1_NR_CLK 61 727 728#endif /* _DT_BINDINGS_CLK_MT8188_H */ 729