Searched refs:CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 (Results 1 - 4 of 4) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dmediatek,mt8188-clk.h393 #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 macro
H A Dmt8195-clk.h467 #define CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1 32 macro
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/mediatek/
H A Dmt8195.dtsi606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3133 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
3288 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
3358 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
H A Dmt8188.dtsi1015 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;

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