Searched refs:JH7110_SYSCLK_UART3_CORE (Results 1 - 3 of 3) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dstarfive,jh7110-crg.h169 #define JH7110_SYSCLK_UART3_CORE 152 macro
/src/sys/arch/riscv/starfive/
H A Djh7110_clkc.c200 #define JH7110_SYSCLK_UART3_CORE 152 macro
612 JH71X0CLKC_GATEDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core",10, "perh_root"),
/src/sys/external/gpl2/dts/dist/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi650 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,

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