Searched refs:PLL1 (Results 1 - 6 of 6) sorted by relevance

/src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/
H A Dqcom,mmcc-msm8960.h128 #define PLL1 117 macro
H A Dstm32mp13-clks.h21 #define PLL1 6 macro
H A Dstm32mp1-clks.h185 #define PLL1 176 macro
/src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/st/
H A Dste-nomadik-stn8815.dtsi196 * that is parent of TIMCLK, PLL1 and PLL2
218 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */
226 /* HCLK divides the PLL1 with 1,2,3 or 4 */
/src/sys/external/gpl2/dts/dist/arch/mips/boot/dts/ingenic/
H A Dgcw0.dts442 * Put high-speed peripherals under PLL1, such that we can change the
/src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/freescale/
H A Dimx8mp-dhcom-som.dtsi519 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,

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