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    Searched refs:AFMT_60958_0 (Results 1 - 10 of 10) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
dce_stream_encoder.h 66 SRI(AFMT_60958_0, DIG, id), \
189 SE_SF(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\
190 SE_SF(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\
656 uint32_t AFMT_60958_0;
amdgpu_dce_stream_encoder.c 1430 REG_UPDATE_2(AFMT_60958_0,
1479 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_evergreen_hdmi.c 367 WREG32(AFMT_60958_0 + offset,
rv770d.h 812 #define AFMT_60958_0 0x74d4
evergreend.h 669 #define AFMT_60958_0 0x7104
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
amdgpu_dcn10_stream_encoder.c 1364 REG_UPDATE_2(AFMT_60958_0,
1415 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0);
dcn10_stream_encoder.h 53 SRI(AFMT_60958_0, DIG, id), \
122 uint32_t AFMT_60958_0;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1690 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
amdgpu_dce_v11_0.c 1732 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
amdgpu_dce_v6_0.c 1540 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);

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