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    Searched refs:BANK_SELECT (Results 1 - 18 of 18) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_gfxhub_v1_0.c 168 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
172 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
amdgpu_gfxhub_v2_0.c 164 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 12);
168 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL3, BANK_SELECT, 9);
amdgpu_mmhub_v2_0.c 151 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
155 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
amdgpu_mmhub_v1_0.c 187 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
191 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
amdgpu_mmhub_v9_4.c 247 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
251 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
amdgpu_gmc_v7_0.c 663 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
amdgpu_gmc_v8_0.c 885 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field);
sid.h 390 #define BANK_SELECT(x) ((x) << 0)
  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv770.c 919 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
965 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
996 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
rv770d.h 653 #define BANK_SELECT(x) ((x) << 0)
nid.h 123 #define BANK_SELECT(x) ((x) << 0)
cikd.h 506 #define BANK_SELECT(x) ((x) << 0)
sid.h 388 #define BANK_SELECT(x) ((x) << 0)
radeon_evergreen.c 2419 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2472 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
2502 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
evergreend.h 1161 #define BANK_SELECT(x) ((x) << 0)
radeon_ni.c 1309 BANK_SELECT(6) |
radeon_si.c 4320 BANK_SELECT(4) |
radeon_cik.c 5474 BANK_SELECT(4) |

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