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    Searched refs:CLK_READ (Results 1 - 11 of 11) sorted by relevancy

  /src/sys/arch/mvme68k/stand/sboot/
clock.c 107 cl->cl_csr |= CLK_READ; /* enable read (stop time) */
114 cl->cl_csr &= ~CLK_READ; /* time wears on */
clockreg.h 59 #define CLK_READ 0x40 /* want to read (freeze clock) */
  /src/sys/arch/arm/amlogic/
meson_clk_mpll.c 63 val = CLK_READ(sc, mpll->sdm.reg);
66 val = CLK_READ(sc, mpll->n2.reg);
meson_clk_gate.c 53 val = CLK_READ(sc, gate->reg);
meson_clk_mux.c 49 val = CLK_READ(sc, mux->reg);
meson_clk_div.c 60 val = CLK_READ(sc, div->reg);
104 val = CLK_READ(sc, div->reg);
meson_clk_pll.c 62 val = CLK_READ(sc, pll->n.reg);
65 val = CLK_READ(sc, pll->m.reg);
69 val = CLK_READ(sc, pll->frac.reg);
92 if ((CLK_READ(sc, pll->l.reg) & pll->l.mask) != 0)
mesong12_clkc.c 1278 if ((CLK_READ(sc, clk->u.mux.reg) & __BIT(11)) == 0) {
1301 val = CLK_READ(sc, reg_cntl0);
1351 val = CLK_READ(sc, clk->u.mux.reg);
1359 val = CLK_READ(sc, reg_cntl0);
1361 val = CLK_READ(sc, reg_cntl0);
1373 val = CLK_READ(sc, reg_cntl0);
1383 val = CLK_READ(sc, reg_cntl0);
1385 val = CLK_READ(sc, reg_cntl0);
1388 val = CLK_READ(sc, reg_cntl0);
1393 if ((CLK_READ(sc, reg_cntl0) & MESON_PLL_CNTL_REG_LOCK) != 0)
    [all...]
meson8b_clkc.c 122 uint32_t cntl0 = CLK_READ(sc, HHI_SYS_CPU_CLK_CNTL0);
123 uint32_t cntl = CLK_READ(sc, HHI_SYS_PLL_CNTL);
170 } while ((CLK_READ(sc, HHI_SYS_PLL_CNTL) & HHI_SYS_PLL_CNTL_LOCK) == 0);
meson_clk.c 77 const uint32_t val = CLK_READ(sc, reset->reg);
91 const uint32_t val = CLK_READ(sc, reset->reg);
meson_clk.h 390 #define CLK_READ meson_clk_read
394 uint32_t _cwb_tmp_ = CLK_READ((sc), (reg)); \

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