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    Searched refs:DSPCNTR (Results 1 - 8 of 8) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/i915/gvt/
fb_decoder.c 218 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe));
display.c 304 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
handlers.c 773 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
2032 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
2043 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
2054 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
cmd_parser.c 1250 info->ctrl_reg = DSPCNTR(info->pipe);
1316 info->ctrl_reg = DSPCNTR(info->pipe);
  /src/sys/external/bsd/drm2/dist/drm/i915/display/
vlv_dsi.c 1591 val = I915_READ(DSPCNTR(plane->i9xx_plane));
intel_display.c 4116 u32 dspcntr = 0; local in function:i9xx_plane_ctl_crtc
4119 dspcntr |= DISPPLANE_GAMMA_ENABLE;
4122 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
4125 dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe);
4127 return dspcntr;
4137 u32 dspcntr; local in function:i9xx_plane_ctl
4139 dspcntr = DISPLAY_PLANE_ENABLE;
4143 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
4147 dspcntr |= DISPPLANE_8BPP;
4150 dspcntr |= DISPPLANE_BGRX555
4330 u32 dspcntr; local in function:i9xx_update_plane
4392 u32 dspcntr; local in function:i9xx_disable_plane
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/i915/
intel_pm.c 1082 * DSPCNTR[13] supposedly controls whether the
1088 * that either DSPCNTR[13] doesn't do anything, or that
6344 I915_WRITE(DSPCNTR(pipe),
6345 I915_READ(DSPCNTR(pipe)) |
i915_reg.h 6392 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR)

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