| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| renoir_ppt.h | 35 #define GET_DPM_CUR_FREQ(table, clk_type, dpm_level, freq) \
39 freq = table->SocClocks[dpm_level].Freq; \
42 freq = table->MemClocks[dpm_level].Freq; \
45 freq = table->DcfClocks[dpm_level].Freq; \
48 freq = table->FClocks[dpm_level].Freq; \
|
| amdgpu_renoir_ppt.c | 227 * This interface just for getting uclk ultimate freq and should't introduce
231 uint32_t dpm_level, uint32_t *freq)
238 GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq);
586 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
591 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
596 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
601 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| smu10_driver_if.h | 47 uint16_t Freq;
107 uint32_t Freq; /* In MHz */
|
| smu12_driver_if.h | 48 uint16_t Freq; // in MHz
114 uint32_t Freq; // In MHz
|
| smu9_driver_if.h | 123 uint16_t Freq; /* in MHz */
|
| /src/common/dist/zlib/ |
| trees.c | 445 for (n = 0; n < L_CODES; n++) s->dyn_ltree[n].Freq = 0;
446 for (n = 0; n < D_CODES; n++) s->dyn_dtree[n].Freq = 0;
447 for (n = 0; n < BL_CODES; n++) s->bl_tree[n].Freq = 0;
449 s->dyn_ltree[END_BLOCK].Freq = 1;
500 (tree[n].Freq < tree[m].Freq || \
501 (tree[n].Freq == tree[m].Freq && depth[n] <= depth[m]))
533 * IN assertion: the fields freq and dad are set, heap[heap_max] and
573 f = tree[n].Freq;
[all...] |
| deflate.h | 76 ush freq; /* frequency count */ member in union:ct_data_s::__anonf3f70993010a
85 #define Freq fc.freq
339 s->dyn_ltree[cc].Freq++; \
348 s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \
349 s->dyn_dtree[d_code(dist)].Freq++; \
358 s->dyn_ltree[cc].Freq++; \
368 s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \
369 s->dyn_dtree[d_code(dist)].Freq++; \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/ |
| amdgpu_dcn21_resource.c | 1368 {.Freq = 400, .Vol = 1},
1369 {.Freq = 483, .Vol = 1},
1370 {.Freq = 602, .Vol = 1},
1371 {.Freq = 738, .Vol = 1} },
1373 {.Freq = 300, .Vol = 1},
1374 {.Freq = 400, .Vol = 1},
1375 {.Freq = 400, .Vol = 1},
1376 {.Freq = 400, .Vol = 1} },
1378 {.Freq = 400, .Vol = 1},
1379 {.Freq = 800, .Vol = 1}
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dm_pp_smu.h | 118 * fixed clock at requested freq, either from FCH bypass or DFS
155 // voltage managed SMU, freq set by driver
162 // freq/voltage managed by SMU
178 * fixed clock at requested freq, either from FCH bypass or DFS
252 uint32_t Freq; // In MHz
|
| /src/sys/net/ |
| zlib.c | 338 ush freq; /* frequency count */ member in union:ct_data_s::__anon0201f153010a
347 #define Freq fc.freq
586 s->dyn_ltree[cc].Freq++; \
595 s->dyn_ltree[_length_code[len]+LITERALS+1].Freq++; \
596 s->dyn_dtree[d_code(dist)].Freq++; \
2513 for (n = 0; n < L_CODES; n++) s->dyn_ltree[n].Freq = 0;
2514 for (n = 0; n < D_CODES; n++) s->dyn_dtree[n].Freq = 0;
2515 for (n = 0; n < BL_CODES; n++) s->bl_tree[n].Freq = 0;
2517 s->dyn_ltree[END_BLOCK].Freq = 1
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/clk_mgr/dcn21/ |
| amdgpu_rn_clk_mgr.c | 633 return clock_table->DcfClocks[i].Freq;
651 if (clock_table->FClocks[i].Freq != 0) {
666 bw_params->clk_table.entries[i].fclk_mhz = clock_table->FClocks[j].Freq;
667 bw_params->clk_table.entries[i].memclk_mhz = clock_table->MemClocks[j].Freq;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| amdgpu_smu10_hwmgr.c | 432 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
457 if (0 == result && table->DcefClocks[0].Freq != 0) {
590 if (min_mclk < data->clock_table.FClocks[0].Freq)
591 min_mclk = data->clock_table.FClocks[0].Freq;
|
| amdgpu_vega10_hwmgr.c | 1902 pp_table->DisplayClockTable[disp_clock][i].Freq =
1909 pp_table->DisplayClockTable[disp_clock][i].Freq =
|
