| /src/sys/external/bsd/drm/dist/shared-core/ |
| i915_suspend.c | 40 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
42 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
61 array[i] = I915_READ(reg + (i << 2));
253 dev_priv->saveDSPARB = I915_READ(DSPARB);
256 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
257 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
258 dev_priv->saveFPA0 = I915_READ(FPA0);
259 dev_priv->saveFPA1 = I915_READ(FPA1);
260 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
262 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD)
[all...] |
| i915_irq.c | 62 (void) I915_READ(IMR);
73 (void) I915_READ(IMR);
96 (void) I915_READ(reg);
108 (void) I915_READ(reg);
127 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
157 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
159 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
161 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
180 return I915_READ(reg);
192 iir = I915_READ(IIR)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/ |
| i915_suspend.c | 46 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
50 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
82 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
85 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
90 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
91 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
94 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
97 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
100 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
101 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i))
[all...] |
| i915_debugfs.c | 410 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
413 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
416 I915_READ(GEN8_DE_PIPE_IER(pipe)));
422 I915_READ(GEN8_DE_PORT_IMR));
424 I915_READ(GEN8_DE_PORT_IIR));
426 I915_READ(GEN8_DE_PORT_IER));
429 I915_READ(GEN8_DE_MISC_IMR));
431 I915_READ(GEN8_DE_MISC_IIR));
433 I915_READ(GEN8_DE_MISC_IER));
436 I915_READ(GEN8_PCU_IMR))
[all...] |
| intel_device_info.c | 252 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
254 dss_en = I915_READ(GEN12_GT_DSS_ENABLE);
257 eu_en_fuse = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
280 s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
281 ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
282 eu_en = ~(I915_READ(GEN11_EU_DISABLE) & GEN11_EU_DIS_MASK);
295 const u32 fuse2 = I915_READ(GEN8_FUSE2);
306 eu_en = ~I915_READ(GEN8_EU_DISABLE0);
311 eu_en = ~I915_READ(GEN8_EU_DISABLE1);
318 eu_en = ~I915_READ(GEN8_EU_DISABLE2)
[all...] |
| i915_drv.c | 853 val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
858 val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
897 val = I915_READ(SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
928 val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
1032 val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
1054 val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
2248 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
2249 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
2250 s->arb_mode = I915_READ(ARB_MODE);
2251 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0)
[all...] |
| i915_irq.c | 272 val = I915_READ(PORT_HOTPLUG_EN);
349 old_val = I915_READ(GEN8_DE_PORT_IMR);
403 u32 sdeimr = I915_READ(SDEIMR);
656 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
931 misccpctl = I915_READ(GEN7_MISCCPCTL);
946 error_status = I915_READ(reg);
1250 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1258 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1259 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1260 I915_READ(PIPE_CRC_RES_3_IVB(pipe))
[all...] |
| intel_pm.c | 69 I915_READ(CHICKEN_PAR1_1) |
75 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
79 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
83 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
88 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
93 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL)
103 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
110 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
117 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
138 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0)
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_combo_phy.c | 56 val = I915_READ(ICL_PORT_COMP_DW3(phy));
89 val = I915_READ(ICL_PORT_COMP_DW1(phy));
102 u32 val = I915_READ(reg);
135 return !(I915_READ(CHICKEN_MISC_2) & CNL_COMP_PWR_DOWN) &&
136 (I915_READ(CNL_PORT_COMP_DW0) & COMP_INIT);
159 val = I915_READ(CHICKEN_MISC_2);
166 val = I915_READ(CNL_PORT_COMP_DW0);
170 val = I915_READ(CNL_PORT_CL1CM_DW5);
182 val = I915_READ(CHICKEN_MISC_2);
192 return I915_READ(ICL_PORT_COMP_DW0(phy)) & COMP_INIT
[all...] |
| icl_dsi.c | 47 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
54 return (I915_READ(DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
117 if (wait_for_us(!(I915_READ(DSI_LP_MSG(dsi_trans)) &
166 tmp = I915_READ(DSI_CMD_TXHDR(dsi_trans));
220 tmp = I915_READ(ICL_PORT_TX_DW5_LN0(phy));
227 tmp = I915_READ(ICL_PORT_TX_DW5_AUX(phy));
234 tmp = I915_READ(ICL_PORT_TX_DW2_LN0(phy));
242 tmp = I915_READ(ICL_PORT_TX_DW2_AUX(phy));
250 tmp = I915_READ(ICL_PORT_TX_DW4_AUX(phy));
260 tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, phy))
[all...] |
| vlv_dsi.c | 119 u32 val = I915_READ(reg);
234 if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))
336 tmp = I915_READ(MIPI_CTRL(port));
341 tmp = I915_READ(MIPI_CTRL(PORT_A));
347 tmp = I915_READ(MIPI_CTRL(port));
348 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))
365 !(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY);
386 val = I915_READ(MIPI_CTRL(PORT_A));
391 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {
392 val = I915_READ(MIPI_DEVICE_READY(port))
[all...] |
| intel_audio.c | 299 tmp = I915_READ(reg_eldv);
305 tmp = I915_READ(reg_elda);
310 if (I915_READ(reg_edid) != *((const u32 *)eld + i))
325 tmp = I915_READ(G4X_AUD_VID_DID);
332 tmp = I915_READ(G4X_AUD_CNTL_ST);
350 tmp = I915_READ(G4X_AUD_VID_DID);
362 tmp = I915_READ(G4X_AUD_CNTL_ST);
372 tmp = I915_READ(G4X_AUD_CNTL_ST);
396 tmp = I915_READ(HSW_AUD_CFG(cpu_transcoder));
410 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(cpu_transcoder))
[all...] |
| intel_dpll_mgr.c | 388 val = I915_READ(PCH_DPLL(id));
390 hw_state->fp0 = I915_READ(PCH_FP0(id));
391 hw_state->fp1 = I915_READ(PCH_FP1(id));
414 val = I915_READ(PCH_DREF_CONTROL);
533 val = I915_READ(WRPLL_CTL(id));
551 val = I915_READ(SPLL_CTL);
576 val = I915_READ(WRPLL_CTL(id));
596 val = I915_READ(SPLL_CTL);
999 val = I915_READ(DPLL_CTRL1);
1025 I915_READ(regs[id].ctl) | LCPLL_PLL_ENABLE)
[all...] |
| vlv_dsi_pll.c | 209 val = I915_READ(BXT_DSI_PLL_ENABLE);
223 val = I915_READ(BXT_DSI_PLL_CTL);
246 val = I915_READ(BXT_DSI_PLL_ENABLE);
333 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL);
351 temp = I915_READ(MIPI_CTRL(port));
420 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
530 val = I915_READ(BXT_DSI_PLL_ENABLE);
552 tmp = I915_READ(BXT_MIPI_CLOCK_CTL);
559 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1);
563 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2)
[all...] |
| intel_ddi.c | 826 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
847 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
868 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1041 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
1187 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1195 temp = I915_READ(DP_TP_STATUS(PORT_E));
1214 temp = I915_READ(DDI_BUF_CTL(PORT_E));
1220 temp = I915_READ(DP_TP_CTL(PORT_E));
1229 temp = I915_READ(FDI_RX_MISC(PIPE_A));
1282 wrpll = I915_READ(reg)
[all...] |
| intel_display_power.c | 316 ret = I915_READ(regs->bios) & req_mask ? 1 : 0;
317 ret |= I915_READ(regs->driver) & req_mask ? 2 : 0;
319 ret |= I915_READ(regs->kvmr) & req_mask ? 4 : 0;
320 ret |= I915_READ(regs->debug) & req_mask ? 8 : 0;
342 wait_for((disabled = !(I915_READ(regs->driver) &
384 val = I915_READ(regs->driver);
392 val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx));
415 val = I915_READ(regs->driver);
433 val = I915_READ(regs->driver);
437 val = I915_READ(ICL_PORT_CL_DW12(phy))
[all...] |
| intel_dpio_phy.c | 286 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
290 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
295 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
305 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
310 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
322 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
325 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
333 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
345 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
381 val = I915_READ(BXT_P_CR_GT_DISP_PWRON)
[all...] |
| intel_cdclk.c | 245 tmp = I915_READ(IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ?
415 u32 lcpll = I915_READ(LCPLL_CTL);
420 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
528 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
695 u32 lcpll = I915_READ(LCPLL_CTL);
700 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
727 if (WARN((I915_READ(LCPLL_CTL) &
742 val = I915_READ(LCPLL_CTL);
750 if (wait_for_us(I915_READ(LCPLL_CTL) &
754 val = I915_READ(LCPLL_CTL)
[all...] |
| intel_dvo.c | 145 tmp = I915_READ(intel_dvo->dev.dvo_reg);
160 tmp = I915_READ(intel_dvo->dev.dvo_reg);
176 tmp = I915_READ(intel_dvo->dev.dvo_reg);
198 u32 temp = I915_READ(dvo_reg);
202 I915_READ(dvo_reg);
212 u32 temp = I915_READ(dvo_reg);
219 I915_READ(dvo_reg);
294 dvo_val = I915_READ(dvo_reg) &
489 dpll[pipe] = I915_READ(DPLL(pipe));
|
| intel_panel.c | 549 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
556 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
565 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
584 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
600 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
619 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
629 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
657 tmp = I915_READ(BLC_PWM_CTL) & ~mask;
668 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
760 tmp = I915_READ(BLC_PWM_CPU_CTL2)
[all...] |
| intel_fifo_underrun.c | 103 if ((I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0)
129 if (old && I915_READ(reg) & PIPE_FIFO_UNDERRUN_STATUS)
151 u32 err_int = I915_READ(GEN7_ERR_INT);
181 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
217 u32 serr_int = I915_READ(SERR_INT);
249 if (old && I915_READ(SERR_INT) &
|
| intel_display.c | 531 I915_READ(CLKGATE_DIS_PSL(pipe)) |
535 I915_READ(CLKGATE_DIS_PSL(pipe)) &
546 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS);
549 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS);
1061 line1 = I915_READ(reg) & line_mask;
1063 line2 = I915_READ(reg) & line_mask;
1115 val = I915_READ(DPLL(pipe));
1151 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1154 u32 val = I915_READ(FDI_TX_CTL(pipe));
1170 val = I915_READ(FDI_RX_CTL(pipe))
[all...] |
| intel_lvds.c | 93 val = I915_READ(lvds_reg);
133 tmp = I915_READ(lvds_encoder->reg);
151 tmp = I915_READ(PFIT_CONTROL);
164 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
166 val = I915_READ(PP_ON_DELAYS(0));
171 val = I915_READ(PP_OFF_DELAYS(0));
175 val = I915_READ(PP_DIVISOR(0));
211 val = I915_READ(PP_CONTROL(0));
321 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
323 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON)
[all...] |
| intel_crt.c | 83 val = I915_READ(adpa_reg);
120 tmp = I915_READ(crt->adpa_reg);
450 save_adpa = adpa = I915_READ(crt->adpa_reg);
472 adpa = I915_READ(crt->adpa_reg);
506 save_adpa = adpa = I915_READ(crt->adpa_reg);
520 adpa = I915_READ(crt->adpa_reg);
569 stat = I915_READ(PORT_HOTPLUG_STAT);
714 u32 vsync = I915_READ(vsync_reg);
926 adpa = I915_READ(crt->adpa_reg);
977 adpa = I915_READ(adpa_reg)
[all...] |
| intel_dsb.c | 50 return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id));
60 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
80 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id));
|
