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Searched refs:MC_CG_ARB_FREQ_F0 (Results 1 - 10 of 10) sorted by relevancy

/src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_rv730_dpm.c	`36 #define MC_CG_ARB_FREQ_F0 0x0a 363 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;`
radeon_ni_dpm.c	`40 #define MC_CG_ARB_FREQ_F0 0x0a 1519 case MC_CG_ARB_FREQ_F0: 1544 case MC_CG_ARB_FREQ_F0: 1596 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 1613 if (tmp == MC_CG_ARB_FREQ_F0) 1616 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);`
radeon_cypress_dpm.c	`41 #define MC_CG_ARB_FREQ_F0 0x0a 1284 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;`
radeon_rv770_dpm.c	`39 #define MC_CG_ARB_FREQ_F0 0x0a 1070 table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;`
radeon_ci_dpm.c	`41 #define MC_CG_ARB_FREQ_F0 0x0a 2480 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 2495 if (tmp == MC_CG_ARB_FREQ_F0) 2498 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);`
radeon_btc_dpm.c	`41 #define MC_CG_ARB_FREQ_F0 0x0a 1415 table->ULVState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;`
radeon_si_dpm.c	`40 #define MC_CG_ARB_FREQ_F0 0x0a 4249 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4271 if (tmp == MC_CG_ARB_FREQ_F0) 4274 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
amdgpu_smu7_hwmgr.c	`63 #define MC_CG_ARB_FREQ_F0 0x0a 465 case MC_CG_ARB_FREQ_F0: 480 case MC_CG_ARB_FREQ_F0: 517 MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 528 if (tmp == MC_CG_ARB_FREQ_F0) 532 tmp, MC_CG_ARB_FREQ_F0);`
/src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_si_dpm.c	`46 #define MC_CG_ARB_FREQ_F0 0x0a 3095 case MC_CG_ARB_FREQ_F0: 3120 case MC_CG_ARB_FREQ_F0: 4715 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4737 if (tmp == MC_CG_ARB_FREQ_F0) 4740 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);`
/src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
amdgpu_ci_smumgr.c	`63 #define MC_CG_ARB_FREQ_F0 0x0a`

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