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  /src/sys/external/bsd/drm2/dist/drm/radeon/
radeon_cik.c 1719 * (CIK).
1742 * requested doorbell index (CIK).
1767 * requested doorbell index (CIK).
1883 * Load the GDDR MC ucode into the hw (CIK).
2344 * surface uses those parameters (CIK).
2348 u32 *tile = rdev->config.cik.tile_mode_array;
2349 u32 *macrotile = rdev->config.cik.macrotile_mode_array;
2351 ARRAY_SIZE(rdev->config.cik.tile_mode_array);
2353 ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
2356 u32 num_rbs = rdev->config.cik.max_backends_per_se
    [all...]
radeon_kms.c 295 *value = rdev->config.cik.tile_config;
349 *value = rdev->config.cik.max_backends_per_se *
350 rdev->config.cik.max_shader_engines;
369 *value = rdev->config.cik.max_tile_pipes;
389 *value = rdev->config.cik.backend_map;
418 *value = rdev->config.cik.max_cu_per_sh;
444 *value = rdev->config.cik.max_shader_engines;
456 *value = rdev->config.cik.max_sh_per_se;
491 value = rdev->config.cik.tile_mode_array;
503 value = rdev->config.cik.macrotile_mode_array
    [all...]
Makefile 76 si_blit_shaders.o radeon_prime.o cik.o cik_blit_shaders.o \
radeon_atombios_crtc.c 1307 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1363 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
radeon.h 831 struct cik_irq_stat_regs cik; member in union:radeon_irq_stat_regs
902 /* for CIK queues */
2246 struct cik_asic cik; member in union:radeon_asic_config
2463 const struct firmware *mec_fw; /* CIK MEC firmware */
2465 const struct firmware *sdma_fw; /* CIK SDMA firmware */
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
Makefile 63 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \

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