| /src/sys/arch/vax/boot/boot/ |
| consio.c | 48 void pr_putchar(int c); /* putchar() using mtpr/mfpr */
130 * mtpr/mfpr are restricted to serial consoles, ROM-based routines
196 while (mfpr(PR_RXCS) & GC_DON) {
197 if ((mfpr(PR_RXDB) & 0x7f) == 19) {
199 while ((mfpr(PR_RXCS) & GC_DON) == 0)
201 if ((mfpr(PR_RXDB) & 0x7f) == 17)
207 while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
214 * getchar() using MFPR
219 while ((mfpr(PR_RXCS) & GC_DON) == 0)
221 return (mfpr(PR_RXDB)); /* now get it *
[all...] |
| ctu.c | 107 while ((mfpr(PR_CSRS) & 0x80) == 0)
110 status = mfpr(PR_CSRD);
148 while ((mfpr(PR_CSTS) & 0x80) == 0)
|
| /src/sys/arch/vax/vax/ |
| ka670.c | 131 if (mfpr(PR_PCSTS) & KA670_PCS_TRAP2) {
162 snprintb(sbuf, sizeof(sbuf), KA670_PCSTS_BITS, mfpr(PR_PCSTS));
165 snprintb(sbuf, sizeof(sbuf), KA670_BCSTS_BITS, mfpr(PR_BCSTS));
178 val = mfpr(PR_PCSTS);
188 snprintb(sbuf, sizeof(sbuf), KA670_PCSTS_BITS, mfpr(PR_PCSTS));
191 snprintb(sbuf, sizeof(sbuf), KA670_BCSTS_BITS, mfpr(PR_BCSTS));
|
| ka49.c | 80 { volatile int *hej = (void *)mfpr(PR_ISP); *hej = *hej; hej[-1] = hej[-1];}
144 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
149 mtpr(mfpr(PR_CCTL) | 0x10, PR_CCTL); /* Set cache size */
150 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
151 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
152 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
161 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
171 mtpr(mfpr(PR_CCTL) | 0x10 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
|
| ka53.c | 84 volatile int *hej = (void *)mfpr(PR_ISP);
159 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
164 mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
165 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
166 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
167 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
177 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
187 mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
|
| ka680.c | 108 volatile int *hej = (void *)mfpr(PR_ISP);
155 mtpr(mfpr(PR_CCTL) | CCTL_SW_ETM, PR_CCTL);
160 mtpr(mfpr(PR_CCTL) | 6, PR_CCTL); /* Set cache size and speed */
161 mtpr(mfpr(PR_BCETSTS), PR_BCETSTS); /* Clear error bits */
162 mtpr(mfpr(PR_BCEDSTS), PR_BCEDSTS); /* Clear error bits */
163 mtpr(mfpr(PR_NESTS), PR_NESTS); /* Clear error bits */
215 mtpr((mfpr(PR_CCTL) & ~(CCTL_SW_ETM|CCTL_ENABLE)) | CCTL_HW_ETM,
224 mtpr(mfpr(PR_CCTL) | 6 | CCTL_ENABLE, PR_CCTL); /* enab. bcache */
|
| lock_stubs.S | 63 mfpr $PR_SSP, %r3 /* set new value (curlwp) */
82 mfpr $PR_SSP, %r2 /* get curlwp (old) */
101 mfpr $PR_IPL, %r2 /* get current IPL */
106 1: mfpr $PR_SSP, %r4 /* get curlwp */
134 mfpr $PR_SSP, %r4 /* get curlwp */
170 mfpr $PR_SSP, %r4
179 mfpr $PR_SSP, %r3 /* get new value (curlwp) */
202 mfpr $PR_SSP, %r4 /* get curlwp */
210 2: mfpr $PR_SSP, %r2 /* get old (curlwp) */
235 mfpr $PR_SSP, %r
[all...] |
| ka88.c | 108 mfpr(PR_SID) & 65535, (mfpr(PR_SID) >> 16) & 127);
244 int c = mfpr(PR_RXCD);
270 while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
282 while ((mfpr(PR_RXCS) & GC_DON) == 0)
284 ret = mfpr(PR_RXDB);
327 ka88_confdata = mfpr(PR_RXDB);
378 ka88_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
379 ka88_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
381 ka88_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB *
[all...] |
| ka43.c | 147 if (mfpr(PR_PCSTS) & KA43_PCS_TRAP2) {
178 snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS));
216 snprintb(sbuf, sizeof(sbuf), KA43_PCSTS_BITS, mfpr(PR_PCSTS));
234 val = mfpr(PR_PCSTS);
|
| gencons.c | 227 i = mfpr(pr_rxdb[sc->unit]) & 0377; /* Mask status flags etc... */
331 while (mfpr(PR_RXCS) & GC_DON) {
332 if ((mfpr(PR_RXDB) & 0x7f) == 19) {
334 while ((mfpr(PR_RXCS) & GC_DON) == 0)
336 if ((mfpr(PR_RXDB) & 0x7f) == 17)
345 while ((mfpr(PR_TXCS) & GC_RDY) == 0) /* Wait until xmit ready */
358 while ((mfpr(PR_RXCS) & GC_DON) == 0) /* Receive chr */
360 i = mfpr(PR_RXDB) & 0x7f;
|
| crl.c | 194 if ((mfpr(PR_STXCS) & STXCS_RDY) == 0)
216 i = mfpr(PR_STXCS);
226 crlstat.crl_ds = mfpr(PR_STXDB);
253 *crltab.crl_xaddr++ = mfpr(PR_STXDB);
266 crlstat.crl_cs = mfpr(PR_STXDB);
|
| ka6400.c | 262 int c = mfpr(PR_RXCD);
290 mtpr(mfpr(PR_PCSTS), PR_PCSTS); /* clear error flags */
345 ka6400_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
346 ka6400_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
348 ka6400_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB */
349 ka6400_txrx(id, "D/I 38 %x\r", mfpr(PR_MAPEN)); /* Enable MM */
|
| ka730.c | 176 mcf->mc3_pc, mcf->mc3_psl, mfpr(PR_MCESR));
186 #define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0) ;
|
| findcpu.c | 60 vax_cpudata = mfpr(PR_SID);
|
| ka750.c | 105 if (mfpr(PR_TODR) == 0) { /* Check for failing battery */
119 if (mfpr(PR_ACCS) & 255) {
261 int mcsr = mfpr(PR_MCSR);
286 #define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0) ;
|
| ka860.c | 106 * NOTE: In assmebly code, the mfpr instruction that reads the ESPD
151 __asm("mtpr $0x27,$0x4e; mfpr $0x4f,%0" : "=g" (mdecc));
154 __asm("mtpr $0x2a,$0x4e; mfpr $0x4f,%0" : "=g" (mear));
155 __asm("mtpr $0x25,$0x4e; mfpr $0x4f,%0" : "=g" (mstat1));
156 __asm("mtpr $0x26,$0x4e; mfpr $0x4f,%0" : "=g" (mstat2));
171 mtpr(mfpr(PR_MERG) | M8600_ICRD, PR_MERG);
295 mtpr(mfpr(PR_MERG) & ~M8600_ICRD, PR_MERG);
310 fpa = mfpr(PR_ACCS);
342 int s = splhigh(), old = mfpr(PR_TXCS);
344 #define WAIT while ((mfpr(PR_TXCS) & GC_RDY) == 0)
[all...] |
| subr.S | 124 mfpr $PR_PCBB,PCB_PADDR(%r0) # save PCB physical address
211 1: mfpr $PR_SSP, %r2 # get curlwp
234 mfpr $PR_IPL,%r0 # splhigh()
324 mfpr $PR_SSP,%r4 /* current LWP */
340 mfpr $PR_IPL,%r1
347 mfpr $PR_SSP,%r6 /* Get curlwp */
471 2: mfpr $PR_ESP,%r2
477 1: mfpr $PR_ESP,%r2
488 mfpr $PR_ESP,%r3
495 1: mfpr $PR_ESP,%r
[all...] |
| ctu.c | 144 #define WAIT while ((mfpr(PR_CSTS) & 0x80) == 0)
265 if ((mfpr(PR_CSRS) & 0x80))
269 return mfpr(PR_CSRD);
279 int status = mfpr(PR_CSRD);
371 #define WAIT while ((mfpr(PR_CSTS) & 0x80) == 0)
433 while ((mfpr(PR_CSTS) & 0x80) == 0)
|
| intvec.S | 271 mfpr $PR_SSP, %r0 # get curlwp
279 mfpr $PR_USP, -(%sp)
280 mfpr $PR_SSP, %r0 /* SSP contains curlwp */
319 mfpr $PR_ICCS,%r0
328 mfpr $PR_SSP, %r0 /* SSP contains curlwp */
357 mfpr $PR_USP, -(%sp)
|
| ka820.c | 153 mastercpu = mfpr(PR_BINID);
448 int c = mfpr(PR_RXCD);
545 ka820_txrx(id, "D/I C %x\r", mfpr(PR_SBR)); /* SBR */
546 ka820_txrx(id, "D/I D %x\r", mfpr(PR_SLR)); /* SLR */
548 ka820_txrx(id, "D/I 11 %x\r", mfpr(PR_SCBB)); /* SCB */
549 ka820_txrx(id, "D/I 38 %x\r", mfpr(PR_MAPEN)); /* Enable MM */
|
| /src/sys/arch/vax/boot/xxboot/ |
| bootxx.c | 105 vax_cputype = (mfpr(PR_SID) >> 24) & 0xFF;
395 while (mfpr(PR_RXCS) & GC_DON) {
396 if ((mfpr(PR_RXDB) & 0x7f) == 19) {
398 while ((mfpr(PR_RXCS) & GC_DON) == 0)
400 if ((mfpr(PR_RXDB) & 0x7f) == 17)
406 while ((mfpr(PR_TXCS) & GC_RDY) == 0)
|
| /src/sys/arch/vax/bi/ |
| bi_mainbus.c | 74 sc->sc_intcpu = 1 << mfpr(PR_BINID);
|
| /src/sys/arch/vax/include/ |
| intr.h | 86 return mfpr(PR_IPL);
|
| cpu.h | 157 #define curlwp ((struct lwp *)mfpr(PR_SSP))
174 int ipl = mfpr(PR_IPL);
|
| mtpr.h | 175 mfpr(int reg) function
179 "mfpr %1,%0"
|
