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    Searched refs:mmD4VGA_CONTROL (Results 1 - 15 of 15) sorted by relevancy

  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
amdgpu_dce120_timing_generator.c 409 offset = mmD4VGA_CONTROL - mmD1VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
amdgpu_dce110_timing_generator.c 1826 addr = mmD4VGA_CONTROL;
  /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
amdgpu_dce_v10_0.c 1821 mmD4VGA_CONTROL,
amdgpu_dce_v11_0.c 1863 mmD4VGA_CONTROL,
amdgpu_dce_v6_0.c 1787 mmD4VGA_CONTROL,
amdgpu_dce_v8_0.c 1750 mmD4VGA_CONTROL,
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dce/
dce_6_0_d.h 1046 #define mmD4VGA_CONTROL 0x00F9
dce_8_0_d.h 5149 #define mmD4VGA_CONTROL 0xf9
dce_10_0_d.h 6032 #define mmD4VGA_CONTROL 0xf9
dce_11_0_d.h 6109 #define mmD4VGA_CONTROL 0xf9
dce_11_2_d.h 7783 #define mmD4VGA_CONTROL 0xf9
dce_12_0_offset.h 644 #define mmD4VGA_CONTROL 0x0039
    [all...]
  /src/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/dcn/
dcn_1_0_offset.h 454 #define mmD4VGA_CONTROL 0x0039
    [all...]
dcn_2_1_0_offset.h 142 #define mmD4VGA_CONTROL 0x0039
    [all...]
dcn_2_0_0_offset.h 122 #define mmD4VGA_CONTROL 0x0039
    [all...]

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